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1. 发明申请

WO2006052616A1 STACKED PACKAGING IMPROVEMENTS 审中-公开
标题翻译：堆叠包装改进
公开(公告)号：WO2006052616A1
公开(公告)日：2006-05-18
申请号：PCT/US2005/039716
申请日：2005-11-03
申请人： TESSERA, INC. , HABA, Belgacem , MITCHELL, Craig, S. , BEROZ, Masud
发明人： HABA, Belgacem , MITCHELL, Craig, S. , BEROZ, Masud
IPC分类号： H01L23/498
CPC分类号： H01L24/81 , H01L21/56 , H01L21/78 , H01L23/49575 , H01L23/49833 , H01L24/48 , H01L24/97 , H01L25/105 , H01L25/18 , H01L25/50 , H01L2224/48091 , H01L2224/48227 , H01L2224/97 , H01L2225/1023 , H01L2225/1029 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/01002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/07811 , H01L2924/15311 , H01L2924/19107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A plurality of microelectronic assemblies (60) are made by severing an in-process unit including an upper substrate (40) and lower substrate (20) with microelectronic elements (36) disposed between the substrates. In a further embodiment, a lead frame (452) is joined to a substrate (440) so that the leads project from this substrate. Lead frame (452) is joined to a further substrate (470) with one or more microelectronic elements (436, 404, 406) disposed between the substrates.
摘要翻译：多个微电子组件（60）通过用设置在基板之间的微电子元件（36）切断包括上基板（40）和下基板（20）的在线单元来制造。在另一个实施例中，引线框架（452）连接到基板（440），使得引线从该基板突出。引线框架（452）与设置在基板之间的一个或多个微电子元件（436,404,406）连接到另一基板（470）。

2. 发明申请

WO2007076099A3 MICROELECTRONIC ELEMENTS WITH COMPLIANT TERMINAL MOUNTINGS AND METHODS FOR MAKING THE SAME 审中-公开
公开(公告)号：WO2007076099A3
公开(公告)日：2007-07-05
申请号：PCT/US2006/049202
申请日：2006-12-26
申请人： TESSERA, INC. , HABA, Belgacem , MOHAMMED, Ilyas , MITCHELL, Craig, S. , WARNER, Michael , THOMPSON, Jesse, Burl
发明人： HABA, Belgacem , MOHAMMED, Ilyas , MITCHELL, Craig, S. , WARNER, Michael , THOMPSON, Jesse, Burl
IPC分类号： H01L21/60
摘要： A dielectric structure is formed by a molding process, so that a first surface (32, 432) of a dielectric structure is shaped by contact with the mold. The opposite second surface (34, 434) of the dielectric structure is applied onto the front surface of a wafer element (38, 438). The dielectric structure may include protruding bumps (30, 130, 230) and terminals (44, 144, 244) may be formed on the bumps. The bumps may be of a precise height. The terminals lie at a precisely controlled height above the front surface of the wafer element. The terminals may include projecting posts (213, 413) which extend above a surrounding solder mask layer (248, 448) to facilitate engagement with a test fixture. The posts are immersed within solder joints (274) when the structure is bonded to a circuit panel.

3. 发明申请

WO2007133350A1 SUBSTRATE FOR A MICROELECTRONIC PACKAGE AND METHOD OF FABRICATING THEREOF 审中-公开
标题翻译：一种微电子封装用基板及其制造方法
公开(公告)号：WO2007133350A1
公开(公告)日：2007-11-22
申请号：PCT/US2007/008501
申请日：2007-04-04
申请人： TESSERA, INC. , HABA, Belgacem , MITCHELL, Craig, S. , ALVAREZ, Apolinar
发明人： HABA, Belgacem , MITCHELL, Craig, S. , ALVAREZ, Apolinar
IPC分类号： H01L21/60 , H01L23/02
CPC分类号： H01L25/0657 , H01L21/4853 , H01L23/13 , H01L23/49811 , H01L23/5385 , H01L23/552 , H01L24/48 , H01L25/0652 , H01L25/162 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/48091 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06586 , H01L2924/00014 , H01L2924/01078 , H01L2924/01322 , H01L2924/3025 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Substrates (240) having molded dielectric layers (220) and methods of fabricating such substrates are disclosed. The substrates may include pins (210) extending through the molded layer (220) and may include traces (230) connected to the pins. The substrates may advantageously be used in microelectronic assemblies having high routing density.
摘要翻译：公开了具有模制电介质层（220）的衬底（240）和制造这种衬底的方法。衬底可以包括延伸穿过模制层（220）的销（210），并且可以包括连接到销的迹线（230）。衬底可有利地用于具有高布线密度的微电子组件中。

4. 发明申请

WO2007075678A2 MICROELECTRONIC ASSEMBLIES HAVING VERY FINE PITCH STACKING 审中-公开
标题翻译：具有非常精细的拼接堆叠的微电子组件
公开(公告)号：WO2007075678A2
公开(公告)日：2007-07-05
申请号：PCT/US2006/048423
申请日：2006-12-19
申请人： TESSERA, INC. , HABA, Belgacem , MITCHELL, Craig, S.
发明人： HABA, Belgacem , MITCHELL, Craig, S.
CPC分类号： H01L25/50 , H01L25/0657 , H01L25/105 , H01L2224/16 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/3011 , H01L2924/3511
摘要： A method of making a stacked microelectronic assembly includes providing a first microelectronic package (122A) having a first substrate (124A) and conductive posts (130A) extending from a surface (128A) of the first substrate (124A), and providing a second microelectronic package (122B) having a second substrate (122B) and conductive, fusible masses (148B) extending from a surface (126B) of the second substrate (124B). A microelectronic element (154A) is secured over one of the surfaces of the first and second substrates (124A), (124B), the microelectronic element (154A) defining a vertical height H 1 that extends from the one of the surfaces of the first and second substrate to which the microelectronic element is secured. The tips (131A) of the conductive posts (130A) of the first substrate are abutted against the apexes of the fusible masses (148B) of the second substrate, whereby the vertical height of each conductive post/fusible mass combination is equal to or greater than the vertical height of the microelectronic element (154A) secured to the one of the surfaces of said first and second substrates .
摘要翻译：制造堆叠的微电子组件的方法包括提供具有第一衬底（124A）的第一微电子封装（122A）和从第一衬底（124A）的表面（128A）延伸的导电柱（130A），并且提供第二微电子具有第二基板（122B）和从第二基板（124B）的表面延伸的导电的可熔块（148B）的封装（122B）。微电子元件（154A）固定在第一和第二基板（124A），（124B）的一个表面上，微电子元件（154A）限定垂直高度H 1 微电子元件固定到其上的第一和第二基板的表面之一。第一基板的导电柱（130A）的尖端（131A）抵靠第二基板的可熔块（148B）的顶点，由此每个导电柱/可熔组合的垂直高度等于或大于比固定到所述第一和第二基板的一个表面的微电子元件（154A）的垂直高度高。

5. 发明申请

WO2005031862A1 STRUCTURE AND METHOD OF MAKING SEALED CAPPED CHIPS 审中-公开
标题翻译：密封垫片的结构和方法
公开(公告)号：WO2005031862A1
公开(公告)日：2005-04-07
申请号：PCT/US2004/031299
申请日：2004-09-24
申请人： TESSERA, INC.
发明人： HUMPSTON, Giles , TUCKERMAN, David, B. , MCWILLIAMS, Bruce, M. , HABA, Belgacem , MITCHELL, Craig, S.
IPC分类号： H01L23/10
CPC分类号： H01L23/3114 , B81B2207/095 , B81C1/00293 , B81C1/00301 , B81C2203/0118 , B81C2203/0145 , B81C2203/019 , H01L21/76898 , H01L23/04 , H01L24/11 , H01L24/13 , H01L24/48 , H01L27/14618 , H01L27/14627 , H01L27/14636 , H01L33/62 , H01L2224/0401 , H01L2224/05624 , H01L2224/05644 , H01L2224/11 , H01L2224/11334 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13169 , H01L2224/1401 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/48247 , H01L2224/484 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01061 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15787 , H01L2924/16151 , H01L2924/16195 , H01L2924/16235 , H01L2924/3011 , H01L2924/3025 , H03H3/007 , H03H9/0547 , H03H9/0585 , H03H9/059 , H03H9/1057 , H03H9/1064 , H03H9/1071 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A method of making one or more sealed assemblies is provided which includes assembling a first element to a second element so that a bottom surface of the first element faces downwardly toward a front surface of the second element and a top surface of the first element faces upwardly away from the second element. One or more ring seals are formed to surround one or more regions of the front surface of the second element by introducing flowable material between the first element and the second element from the top surface of the first element through one or more openings in the first element.
摘要翻译：提供了制造一个或多个密封组件的方法，其包括将第一元件组装到第二元件，使得第一元件的底表面向下朝向第二元件的前表面，并且第一元件的顶表面向上远离第二个元素。通过在第一元件和第二元件的顶表面之间通过第一元件中的一个或多个开口引入可流动材料，形成一个或多个环形密封件，以围绕第二元件的前表面的一个或多个区域。

6. 发明申请

WO1997033312A1 METHOD OF ENCAPSULATING A SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：封装半导体封装的方法
公开(公告)号：WO1997033312A1
公开(公告)日：1997-09-12
申请号：PCT/US1997003273
申请日：1997-03-04
申请人： TESSERA, INC.
发明人： TESSERA, INC. , DISTEFANO, Thomas, H. , SMITH, John, W. , FJELSTAD, Joseph , MITCHELL, Craig, S. , KARAVAKIS, Konstantine
IPC分类号： H01L21/56
CPC分类号： H01L21/568 , H01L21/56 , H01L21/565 , H01L21/6835 , H01L23/24 , H01L23/3107 , H01L23/3114 , H01L23/49572 , H01L24/32 , H01L24/50 , H01L24/97 , H01L2224/11003 , H01L2224/83102 , H01L2224/92125 , H01L2224/97 , H01L2924/01015 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01082 , H01L2924/01322 , H01L2924/12042 , H01L2224/86 , H01L2924/00
摘要： A method of encapsulating a semiconductor device. The encapsulation method includes a semiconductor chip package assembly (10) having a spacer (20) layer between a top surface of a sheet-like substrate (16) and a contact bearing surface of a semiconductor chip (12), wherein the substrate (16) has conductive leads (22) thereon, the leads (22) being electrically connected to terminals (26) on a first end and bonded to respective chip contacts (24) on a second end. Typically, the spacer layer (20) is comprised of a compliant or elastomeric material (40). A protective layer (30) is attached on a bottom surface of the substrate (16) so as to cover the terminals (26) on the substrate. A flowable, curable encapsulant material (40) is deposited around a periphery of the semiconductor chip (12) after the attachment of the protective layer (30) so as to encapsulate the leads (22). The encapsulant material (40) is then cured. Typically, this encapsulation method is performed on a plurality of chip assemblies simultaneously.
摘要翻译：一种封装半导体器件的方法。封装方法包括在片状基片（16）的顶表面和半导体芯片（12）的接触支承表面之间具有间隔层（20）的半导体芯片封装组件（10），其中衬底（16））在其上具有导电引线（22），引线（22）在第一端上电连接到端子（26）并且在第二端上结合到相应的芯片触点（24）。通常，间隔层（20）由顺应性或弹性体材料（40）组成。保护层（30）安装在基板（16）的底表面上，以覆盖基板上的端子（26）。在保护层（30）的附着之后，围绕半导体芯片（12）的周边沉积可流动的可固化的密封剂材料（40）以封装引线（22）。密封剂材料（40）然后固化。通常，这种封装方法同时在多个芯片组件上执行。

7. 发明申请

WO2005031861A1 STRUCTURE AND METHOD OF MAKING CAPPED CHIPS INCLUDING A FLOWABLE CONDUCTIVE MEDIUM 审中-公开
标题翻译：制造包括可流动导电介质的封盖的结构和方法
公开(公告)号：WO2005031861A1
公开(公告)日：2005-04-07
申请号：PCT/US2004/031298
申请日：2004-09-24
申请人： TESSERA, INC.
发明人： HUMPSTON, Giles , TUCKERMAN, David, B. , MCWILLIAMS, Bruce, M. , HABA, Belgacem , MITCHELL, Craig, S.
IPC分类号： H01L23/10
CPC分类号： H01L23/3114 , B81B2207/095 , B81C1/00293 , B81C1/00301 , B81C2203/0118 , B81C2203/0145 , B81C2203/019 , H01L21/76898 , H01L23/04 , H01L24/11 , H01L24/13 , H01L24/48 , H01L27/14618 , H01L27/14627 , H01L27/14636 , H01L33/62 , H01L2224/0401 , H01L2224/05624 , H01L2224/05644 , H01L2224/11 , H01L2224/11334 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13169 , H01L2224/1401 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/48247 , H01L2224/484 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01061 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15787 , H01L2924/16151 , H01L2924/16195 , H01L2924/16235 , H01L2924/3011 , H01L2924/3025 , H03H3/007 , H03H9/0547 , H03H9/0585 , H03H9/059 , H03H9/1057 , H03H9/1064 , H03H9/1071 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A structure and method of making a capped chip is provided. A capped chip includes a chip having a front surface, and a plurality of bond pads exposed at the front surface. A cap member has a top surface, a bottom surface opposite the top surface, a plurality of through holes extending between the top and bottom surfaces. The cap member is mounted to the chip such that the bottom surface faces the chip and is spaced therefrom to define a void. A plurality of electrically conductive interconnects extend from the bond pads at least partially through the through holes, the interconnects including a flowable conductive material extending at least partially through the through holes. Further methods are provided of forming a capped chip and simultaneously forming a plurality of capped chips.
摘要翻译：提供制作封盖芯片的结构和方法。封盖芯片包括具有前表面的芯片和暴露在前表面的多个接合焊盘。盖构件具有顶表面，与顶表面相对的底表面，在顶表面和底表面之间延伸的多个通孔。盖构件安装到芯片，使得底表面面向芯片并与其间隔开以限定空隙。多个导电互连件至少部分地通过通孔从接合焊盘延伸，所述互连件包括至少部分延伸穿过通孔的可流动导电材料。提供了形成封盖芯片并同时形成多个封盖芯片的其它方法。

8. 发明申请

WO2005031863A1 STRUCTURE AND METHOD OF MAKING CAPPED CHIPS HAVING VERTICAL INTERCONNECTS 审中-公开
标题翻译：具有垂直互连的封装芯片的结构和方法
公开(公告)号：WO2005031863A1
公开(公告)日：2005-04-07
申请号：PCT/US2004/031453
申请日：2004-09-24
申请人： TESSERA, INC.
发明人： HUMPSTON, Giles , TUCKERMAN, David, B. , MCWILLIAMS, Bruce, M. , HABA, Belgacem , MITCHELL, Craig, S.
IPC分类号： H01L23/10
CPC分类号： H01L23/3114 , B81B2207/095 , B81C1/00293 , B81C1/00301 , B81C2203/0118 , B81C2203/0145 , B81C2203/019 , H01L21/76898 , H01L23/04 , H01L24/11 , H01L24/13 , H01L24/48 , H01L27/14618 , H01L27/14627 , H01L27/14636 , H01L33/62 , H01L2224/0401 , H01L2224/05624 , H01L2224/05644 , H01L2224/11 , H01L2224/11334 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13169 , H01L2224/1401 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/48247 , H01L2224/484 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01061 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15787 , H01L2924/16151 , H01L2924/16195 , H01L2924/16235 , H01L2924/3011 , H01L2924/3025 , H03H3/007 , H03H9/0547 , H03H9/0585 , H03H9/059 , H03H9/1057 , H03H9/1064 , H03H9/1071 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： Capped chips and methods of forming a capped chip are provided in which electrical interconnects are made by conductive elements which extend from bond pads of a chip at least partially through a plurality of through holes of a cap. The electrical interconnects may be solid, so as to form seals extending across the through holes. In some cases, stud bumps extend from the bond pads, forming parts of the electrical interconnects. In some cases, a fusible conductive medium forms a part of the electrical interconnects.
摘要翻译：提供了覆盖芯片和形成封盖芯片的方法，其中电互连通过至少部分地通过盖的多个通孔从芯片的焊盘延伸的导电元件制成。电互连可以是固体的，以便形成延伸穿过通孔的密封件。在一些情况下，螺柱凸起从接合焊盘延伸，形成电互连的部分。在一些情况下，可熔导电介质形成电互连的一部分。

9. 发明申请

WO2003032370A3 STACKED PACKAGES 审中-公开
公开(公告)号：WO2003032370A3
公开(公告)日：2003-04-17
申请号：PCT/US2002/032251
申请日：2002-10-09
申请人： TESSERA, INC.
发明人： PFLUGHAUPT, L., Elliott , GIBSON, David , KIM, Young , MITCHELL, Craig, S.
IPC分类号： H01L23/02
摘要： A stacked chip assembly includes individual units (56) having chips (58) mounted on dielectric layers (20) and traces (38) on the dielectric layers interconnecting the contacts of the chips with terminals (22) disposed in peripheral regions of the dielectric layers. At least some of the traces (38a, 38e) are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls (78) or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traced of the individual units are selectively interrupted, as by breking the individual branches (50), so as to leave chip select contact of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.

10. 发明申请

WO2003032370A2 STACKED PACKAGES 审中-公开
标题翻译：堆叠包装
公开(公告)号：WO2003032370A2
公开(公告)日：2003-04-17
申请号：PCT/US2002/032251
申请日：2002-10-09
申请人： TESSERA, INC.
发明人： PFLUGHAUPT, L., Elliott , GIBSON, David , KIM, Young , MITCHELL, Craig, S.
IPC分类号： H01L
CPC分类号： H01L23/528 , H01L24/48 , H01L25/0657 , H01L2224/05599 , H01L2224/45099 , H01L2224/4824 , H01L2224/85399 , H01L2225/0651 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A stacked chip assembly includes individual units (56) having chips (58) mounted on dielectric layers (20) and traces (38) on the dielectric layers interconnecting the contacts of the chips with terminals (22) disposed in peripheral regions of the dielectric layers. At least some of the traces (38a, 38e) are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls (78) or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traced of the individual units are selectively interrupted, as by breking the individual branches (50), so as to leave chip select contact of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.
摘要翻译：堆叠芯片组件包括具有安装在介电层（20）上的芯片（58）和介电层上的迹线（38）的独立单元（56），所述介电层将芯片的触点与端子（22）设置在介电层的外围区域中。至少一些迹线（38a，38e）是将芯片选择触点连接到芯片选择端子的多分支迹线。单元彼此叠置，不同单元的相应端子通过焊球（78）或其他导电元件彼此连接，以形成垂直总线。在堆叠之前，单个单元的多支路跟踪被选择性地中断，如通过破坏单个分支（50），以便在连接到不同芯片选择端子的不同单元中的芯片的芯片选择接触并由此连接这些芯片到不同的垂直巴士。各个单元理想地是薄的并且彼此直接邻接，以便提供具有来自堆内的切屑的良好热传递的低高度组件。

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