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1. 发明公开

EP1488517A1 PROGRAMMABLE DIFFERENTIAL D FLIP-FLOP 有权
标题翻译：可编程差动D-FLOP
公开(公告)号：EP1488517A1
公开(公告)日：2004-12-22
申请号：EP03744155.7
申请日：2003-03-04
申请人： TERADYNE, INC.
发明人： LING, Kuok
IPC分类号： H03K3/289 , H03K19/094
CPC分类号： H03K3/3562 , H03K3/356043
摘要： A differential D flip-flop is disclosed including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a first current source for generating a fixed bias current in the master cell. The clock circuit having complementary clock inputs to alternatingly set and store data in the data set and data store circuits. The slave cell includes a second differential input coupled to the first differential output of the master cell. The slave cell further includes a second current source for generating a second bias current, the second current source having programmable inputs for varying the slave cell bias current, thereby controlling the delay of the flip-flop.

2. 发明授权

EP1488517B1 PROGRAMMABLE DIFFERENTIAL D FLIP-FLOP 有权
标题翻译：可编程差动D-FLOP
公开(公告)号：EP1488517B1
公开(公告)日：2006-10-04
申请号：EP03744155.7
申请日：2003-03-04
申请人： Teradyne, Inc.
发明人： LING, Kuok
IPC分类号： H03K3/289 , H03K19/094
CPC分类号： H03K3/3562 , H03K3/356043
摘要： A differential D flip-flop is disclosed including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a first current source for generating a fixed bias current in the master cell. The clock circuit having complementary clock inputs to alternatingly set and store data in the data set and data store circuits. The slave cell includes a second differential input coupled to the first differential output of the master cell. The slave cell further includes a second current source for generating a second bias current, the second current source having programmable inputs for varying the slave cell bias current, thereby controlling the delay of the flip-flop.

3. 发明申请

WO2003077421A1 PROGRAMMABLE DIFFERENTIAL D FLIP-FLOP 审中-公开
标题翻译：可编程差分D浮标
公开(公告)号：WO2003077421A1
公开(公告)日：2003-09-18
申请号：PCT/US2003/006466
申请日：2003-03-04
申请人： TERADYNE, INC.
发明人： LING, Kuok
IPC分类号： H03K3/289
CPC分类号： H03K3/3562 , H03K3/356043
摘要： A differential D flip-flop is disclosed including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a first current source for generating a fixed bias current in the master cell. The clock circuit having complementary clock inputs to alternatingly set and store data in the data set and data store circuits. The slave cell includes a second differential input coupled to the first differential output of the master cell. The slave cell further includes a second current source for generating a second bias current, the second current source having programmable inputs for varying the slave cell bias current, thereby controlling the delay of the flip-flop.
摘要翻译：公开了一种差分D触发器，其包括相应的主单元和从单元。主单元包括第一数据集电路和第一数据存储电路。第一数据存储电路耦合到第一数据组电路的输出端。该单元还包括差分时钟电路和用于在主单元中产生固定偏置电流的第一电流源。时钟电路具有互补的时钟输入，以在数据集和数据存储电路中交替地设置和存储数据。从单元包括耦合到主单元的第一差分输出的第二差分输入。从单元还包括用于产生第二偏置电流的第二电流源，第二电流源具有用于改变从单元偏置电流的可编程输入，从而控制触发器的延迟。

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