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1. 发明申请

WO2009089905A1 TELECOM MULTIPLEXER FOR VARIABLE RATE COMPOSITE BIT STREAM 审中-公开
标题翻译：用于可变速率复合位流的电信多路复用器
公开(公告)号：WO2009089905A1
公开(公告)日：2009-07-23
申请号：PCT/EP2008/050408
申请日：2008-01-15
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) , WEGO, Arild , HELLUM, Pål Longva
发明人： WEGO, Arild , HELLUM, Pål Longva
IPC分类号： H04J3/16
CPC分类号： H04J3/1623 , H04J3/1682 , H04J2203/0089
摘要： A multiplexer/demultiplexer (MUX/DEMUX) system for multiplexing and demultiplexing information from a plurality of traffic channels is configured according to a Plesiochronous Digital Hierarchy (PDH) standard into a composite signal transferred to and from a telecommunciations interface (140). A PDH traffic interface (112) receives PDH channel signals from a plurality of PDH channels and a bit-pipe interface (118) receives bit-pipe traffic transported as a packet data stream. A composite signal generation module and interface (124) then creates, outputs and receives a single composite serial data stream including, in a single composite format, informationfrom the received PDH channel signals as well as the packet data stream. The rate of the bit-pipe traffic may be adaptively modulated as a function of the composite rate.
摘要翻译：根据Plesiochronous Digital Hierarchy（PDH）标准将多路复用器/解复用器（MUX / DEMUX）系统复用和解复用来自多个业务信道的信息，被配置成传送到和传送到通信接口（140）的复合信号。 PDH业务接口（112）从多个PDH信道接收PDH信道信号，并且位管接口（118）接收作为分组数据流传送的比特流业务。复合信号产生模块和接口（124）然后以单一复合格式创建，输出和接收包含来自所接收的PDH信道信号以及分组数据流的信息的单个复合串行数据流。位管道流量的速率可以作为复合速率的函数自适应地调制。

2. 发明申请

WO2004059500A1 METHOD FOR REDUCING THE BUS LOAD IN A SYNCHRONOUS DATA BUS SYSTEM 审中-公开
标题翻译：减少同步数据总线系统中总线负载的方法
公开(公告)号：WO2004059500A1
公开(公告)日：2004-07-15
申请号：PCT/NO2002/000497
申请日：2002-12-27
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ) , WEGO, Arild , HELLUM, Pål, Longva , MALVIG, Roar
发明人： WEGO, Arild , HELLUM, Pål, Longva , MALVIG, Roar
IPC分类号： G06F13/40
CPC分类号： G06F13/4054 , G06F13/4072
摘要： The present invention is related to buffering between synchronous circuits communication via a global synchronous bus, and in particular an arrangement for reducing the busload in a TDM bus system by, in a preferred embodiment, introducing a local TEM data bus and an active buffer including a CPU controlled logic between the transceiver loads and the TDM bus. The active buffers in the TX and RX direction together provides a time delay for data travelling from a first local TDM bus out on the backplane TDM bus and back to a second local TDM of the exact duration of one TDM frame or an integer number of TDM frames.
摘要翻译：本发明涉及通过全球同步总线进行的同步电路通信之间的缓冲，特别是用于通过在优选实施例中引入局部TEM数据总线和主动缓冲器来减少TDM总线系统中的总线负载的装置，收发器负载和TDM总线之间的CPU控制逻辑。 TX和RX方向上的主动缓冲器一起为在背板TDM总线上从第一本地TDM总线传出的数据提供时间延迟，并返回到一个TDM帧或整数TDM的确切持续时间的第二本地TDM 帧。

3. 发明授权

EP1532764B1 METHOD AND ARRANGEMENT FOR REDUCING PHASE JUMPS WHEN SWITCHING BETWEEN SYNCHRONISATION SOURCES 有权
标题翻译：用于减少相法和设备跳转时之间切换SYNKRONISATIONSQUELLEN
公开(公告)号：EP1532764B1
公开(公告)日：2009-03-11
申请号：EP02755999.6
申请日：2002-08-30
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)
发明人： WEGO, Arild , HELLUM, Pal, Longva
IPC分类号： H04L7/00 , H04Q11/04
CPC分类号： H03L7/06 , H04J3/0688
摘要： A method and an arrangment for reducing phase jumps in a frame synchronisation signal when switching between synchronisation signal when switching between synchronisation reference sources are disclosed. A new reference signal to which each of the two reference sources (signals) are phase locked, and has frequency n times the respective reference signal, is generated. A selection signal selects the new reference signal to be used, and the selected one is then divided back to its original frequency creating an input signal to a phase-locked loop generating the resulting frame synchronisation signal. In this way, the maximum phase jumps are reduced from one period of the original reference signals to one period of the new reference signal. The invention is particularly applicable for reducing phase jumps on a master frame synchronisation signal in a PDH system.

4. 发明授权

EP1576484B1 METHOD FOR REDUCING THE BUS LOAD IN A SYNCHRONOUS DATA BUS SYSTEM 有权
标题翻译：一种用于减少总线负载在同步通信系统
公开(公告)号：EP1576484B1
公开(公告)日：2006-11-22
申请号：EP02799865.7
申请日：2002-12-27
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)
发明人： WEGO, Arild , HELLUM, Pal, Longva , MALVIG, Roar
IPC分类号： G06F13/40
CPC分类号： G06F13/4054 , G06F13/4072
摘要： The present invention is related to buffering between synchronous circuits communication via a global synchronous bus, and in particular an arrangement for reducing the busload in a TDM bus system by, in a preferred embodiment, introducing a local TEM data bus and an active buffer including a CPU controlled logic between the transceiver loads and the TDM bus. The active buffers in the TX and RX direction together provides a time delay for data travelling from a first local TDM bus out on the backplane TDM bus and back to a second local TDM of the exact duration of one TDM frame or an integer number of TDM frames.

5. 发明授权

EP1535167B1 SWITCHING ARRANGEMENT INCLUDING TIME-SLOT BUSES AND SEVERAL BUFFERS 有权
公开(公告)号：EP1535167B1
公开(公告)日：2005-12-14
申请号：EP02756003.6
申请日：2002-09-06
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)
发明人： WEGO, Arild , HELLUM, Paal, Longva
IPC分类号： G06F13/40 , H04Q11/04
CPC分类号： H04L49/102 , H04L47/50 , H04L47/624 , H04L49/3009 , H04L49/3018 , H04Q11/04 , H04Q2213/13097 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13213 , H04Q2213/13214 , H04Q2213/13292 , H04Q2213/13299 , H04Q2213/13393
摘要： An arrangement for transmitting independent serial data streams through synchronous Time Division Multiplexing (TDM) switches witha number of input and output lines is disclosed. At the receivingside of a switch, there is one data buffer per TDM bus buffering the data before transfer on the bus. A connection table associated with each buffer includes entries addressing the bytes in the buffer. The order of the addresses determines the order of the bytes as they are transferred over the bus. Also, at the transmitting side, there is one data buffer per bus, but only one common connection table. The connection table is divided into one memory area per output line, and determines the order of the data bytes, as they will occur at the respective output lines.

6. 发明授权

EP2245774B1 TELECOM MULTIPLEXER FOR VARIABLE RATE COMPOSITE BIT STREAM 有权
标题翻译： TELEKOM多路复用器，用于复合STREAM可变速率
公开(公告)号：EP2245774B1
公开(公告)日：2012-01-04
申请号：EP08707905.9
申请日：2008-01-15
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： WEGO, Arild , HELLUM, Pål Longva
IPC分类号： H04J3/16
CPC分类号： H04J3/1623 , H04J3/1682 , H04J2203/0089
摘要： A multiplexer/demultiplexer (MUX/DEMUX) system for multiplexing and demultiplexing information from a plurality of traffic channels is configured according to a Plesiochronous Digital Hierarchy (PDH) standard into a composite signal transferred to and from a telecommunciations interface (140). A PDH traffic interface (112) receives PDH channel signals from a plurality of PDH channels and a bit-pipe interface (118) receives bit-pipe traffic transported as a packet data stream. A composite signal generation module and interface (124) then creates, outputs and receives a single composite serial data stream including, in a single composite format, informationfrom the received PDH channel signals as well as the packet data stream. The rate of the bit-pipe traffic may be adaptively modulated as a function of the composite rate.

7. 发明公开

EP2245774A1 TELECOM MULTIPLEXER FOR VARIABLE RATE COMPOSITE BIT STREAM 有权
标题翻译： TELEKOM多路复用器，用于复合STREAM可变速率
公开(公告)号：EP2245774A1
公开(公告)日：2010-11-03
申请号：EP08707905.9
申请日：2008-01-15
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： WEGO, Arild , HELLUM, Pål Longva
IPC分类号： H04J3/16
CPC分类号： H04J3/1623 , H04J3/1682 , H04J2203/0089
摘要： A multiplexer/demultiplexer (MUX/DEMUX) system for multiplexing and demultiplexing information from a plurality of traffic channels is configured according to a Plesiochronous Digital Hierarchy (PDH) standard into a composite signal transferred to and from a telecommunciations interface (140). A PDH traffic interface (112) receives PDH channel signals from a plurality of PDH channels and a bit-pipe interface (118) receives bit-pipe traffic transported as a packet data stream. A composite signal generation module and interface (124) then creates, outputs and receives a single composite serial data stream including, in a single composite format, informationfrom the received PDH channel signals as well as the packet data stream. The rate of the bit-pipe traffic may be adaptively modulated as a function of the composite rate.

8. 发明授权

EP1459186B1 RATE ADAPTATION WITHIN A TDM SWITCH USING BIT STUFFING 有权
标题翻译：速率调整以TDM调解使用位STOP FUNG
公开(公告)号：EP1459186B1
公开(公告)日：2010-09-15
申请号：EP02789031.8
申请日：2002-12-18
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： WEGO, Arild , HELLUM, P l, Longva
IPC分类号： G06F13/00 , H04L7/02 , H04Q11/04
CPC分类号： H04J3/0623

9. 发明授权

EP1340330B1 AN ARRANGEMENT AND METHOD FOR TRANSMITTING DATA OVER A TDM BUS 有权
标题翻译：方法和设备进行数据传输通过TDM总线
公开(公告)号：EP1340330B1
公开(公告)日：2007-09-12
申请号：EP01990486.1
申请日：2001-12-04
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)
发明人： WEGO, Arild
IPC分类号： H04J3/00
CPC分类号： H04J3/0691 , H04L12/403
摘要： The invention relates to a TDM backplane bus system, in which a Frame Synchronisation signal is developed from an external communication signal, a data clock signal is produced from a free running clock oscillator independent of the FS signal, to select the frequency of said clock signal so that the number of periods within a frame is always at least one more than the number of timeslots required, to synchronize the FS signal to the CLK signal, and supply this synchronised Frame Synchronising signal (FS-S) to the TDM-bus. Further, said exceeding period(s) is identified by introducing a carry bit in the timeslot counters, said carry bit being set each time the counter(s) exceeds the number of timeslots on the TDM bus.

10. 发明公开

EP1461917A1 METHOD FOR REDUCING THE AMOUNT OF NEEDED MEMORY IN A TDM SWITCH SYSTEM 有权
标题翻译：一种用于减少所需的存储量以TDM识别系统
公开(公告)号：EP1461917A1
公开(公告)日：2004-09-29
申请号：EP02783862.2
申请日：2002-12-10
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： WEGO, Arild , HELLUM, P l, Longva
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04Q11/0421 , H04Q2213/13103 , H04Q2213/13213 , H04Q2213/13292 , H04Q2213/13361
摘要： The present invention discloses an arrangement providing a better utilization of the bus buffer memory in a data node, e.g. a switch. By using one scheduler on both sides of the switch and one timer for each output and input lines in an inventive way for transferring data to and from the time slot buses in the switch, the memory recourses therein are utilized in a more optimal way, also the present invention. Also, by setting up the scheduler parameters in a special way it is possible to obtain very short delays through the TDM switch. The present invention allows for both structured modus (bytes in transfer on the time slot buses are made identifiable) with constant delay and dependent timing, and for unstructured modus with minimum delay and both independent and dependent timing. This contributes to make the invention very useful and unique.

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