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1. 发明申请

WO2014154497A1 SPIN TORQUE MAGNETIC INTEGRATED CIRCUIT 审中-公开
标题翻译：旋转扭矩磁性集成电路
公开(公告)号：WO2014154497A1
公开(公告)日：2014-10-02
申请号：PCT/EP2014/054985
申请日：2014-03-13
申请人： TECHNISCHE UNIVERSITÄT WIEN
发明人： MAHMOUDI, Hiwa , SELBERHERR, Siegfried , SVERDLOV, Viktor , WINDBACHER, Thomas
IPC分类号： B82Y25/00 , G01R33/09 , G11B5/39 , H01F10/32 , G11C11/15 , H01F41/30 , H01L43/08 , H01L43/12
CPC分类号： H01L43/08 , G01R33/093 , G01R33/098 , G01R33/1284 , G11C11/161 , H01F10/3254 , H01F10/329 , H01L43/10
摘要： The invention relates to a spin torque magnetic integrated circuit (1), comprising a shared free layer (2) with a magnetic anisotropy such as a shape anisotropy or a crystal anisotropy with at least two stable magnetic states disposed on a substrate, a first non-magnetic layer (3) disposed on a first side of the free layer (2), input regions disposed on the non-magnetic layer (3), at least one output region (5) disposed on the non-magnetic layer (3), comprising at least one output layer (6), capping layers (8) to electrically contact the input regions (4a, 4b) and output region (5), wherein two input regions (4a, 4b) are disposed on the non-magnetic layer (3), at least one of the input regions (4a, 4b) comprises at least one magnetic input reference layer (6), and the orientation of the magnetization vectors of the input reference layers, the output reference layer, and the orientation of the magnetic anisotropy of the free layer are collinear. The invention further relates to a flip flop circuit comprising such a circuit, a shift register comprising such a flip flop, and methods to operate these circuits.
摘要翻译：本发明涉及一种自旋转矩磁集成电路（1），其包括具有磁各向异性的共享自由层（2），其具有形状各向异性或具有设置在衬底上的至少两个稳定磁状态的晶体各向异性，第一非 - 设置在自由层（2）的第一侧的磁性层（3），设置在非磁性层（3）上的输入区域，设置在非磁性层（3）上的至少一个输出区域（5），包括至少一个输出层（6），与所述输入区域（4a，4b）和输出区域（5）电接触的封盖层（8），其中两个输入区域（4a，4b）设置在非磁性层（3）中的至少一个输入区域（4a，4b）包括至少一个磁性输入参考层（6），并且输入参考层，输出参考层和取向的自由层的磁各向异性是共线的。本发明还涉及包括这种电路的触发器电路，包括这种触发器的移位寄存器以及操作这些电路的方法。

2. 发明申请

WO2020053277A1 COMPUTER-IMPLEMENTED METHOD AND ELECTRONIC DEVICE FOR DETECTING INFLUENTIAL COMPONENTS IN A NETLIST REPRESENTING AN ELECTRICAL CIRCUIT 审中-公开
公开(公告)号：WO2020053277A1
公开(公告)日：2020-03-19
申请号：PCT/EP2019/074226
申请日：2019-09-11
申请人： TECHNISCHE UNIVERSITÄT WIEN
发明人： MAHMOUDI, Hiwa , ZIMMERMANN, Horst
IPC分类号： G06F17/50
摘要： A computer-implemented method and an electronic device for detecting, in an electrical circuit (1) with electrical components (M g ) subject to variations (δ) of their model parameters (x j ), those components (M g *) the model parameter variations (δ) of which have the strongest influence on a performance (y n ) of the circuit (1), comprising: providing (2) a topology (Q) of the circuit (1) and the model parameters (x j ) of all components (M g ) therein; determining (3), therefrom, topological patterns (P k ) of interconnected components (M g ); generating (4) variation samples (v n ), each comprising a different set of candidate variations (x' j ) of the model parameters (x j ); calculating (5), for each variation sample (v n ), the circuit's performance (y n ) and a deviation from a standard performance and forming a deviation vector (y D ) therefrom; and using the variation samples (v n ), the deviation vector (y D ) and the topological patterns (P k ) in a regression model for detecting (6) the most influential components (M g *).

3. 发明申请

WO2014079747A1 RRAM IMPLICATION LOGIC GATES 审中-公开
标题翻译： RRAM影响逻辑门
公开(公告)号：WO2014079747A1
公开(公告)日：2014-05-30
申请号：PCT/EP2013/073707
申请日：2013-11-13
申请人： TECHNISCHE UNIVERSITÄT WIEN
发明人： MAHMOUDI, Hiwa , WINDBACHER, Thomas , SVERDLOV, Viktor , SELBERHERR, Siegfried
IPC分类号： G11C11/16 , G11C13/00 , H03K19/177
CPC分类号： G11C11/16 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C13/0028 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0078 , G11C2213/79 , H03K19/177
摘要： The invention relates to an electronic circuit (200, 400) comprising a plurality of bit cells (210, 410) arranged in an array and being selectable by row lines (222, 422) and column lines (232, 432), at least one row driver (220, 420), at least one column driver (230, 430), and a readout circuit (260, 460), wherein each bit cell (210, 410) comprises an access transistor (214, 414) and a non-volatile resistive- switching element (212, 412) with at least two resistance states, wherein, in order to write a new data (T_n+1) in a target bit cell (T), said new data depending on a data (S_n) of a source bit cell (S) and on a data (T_n) stored by the target bit cell (T) before sad writing, the row driver (220, 420) and the column driver (230, 430) are capable to simultaneously apply a first selecting voltage (V_s) to a first row line (222, 422) to select the target bit cell (210, 410), a secod selecting voltage (V_p-s) to a second row line (222', 422') to select the source bit cell (210', 410'), and a logic current (l imp) to at least one column line (232, 432), wherein the first selecting voltage (V_s) is higher than the second selecting voltage (V_p-s), such that in response to the voltages applied to the target and source bit cells, the access transistor of the target bit cell ha a lower resistance than the access transistor of the source bit cell.
摘要翻译：本发明涉及一种电子电路（200,400），其包括以阵列布置并可由行线（222,422）和列线（232,432）选择的多个位单元（210,410），至少一个行驱动器（220,420），至少一个列驱动器（230,430）和读出电路（260,460），其中每个位单元（210,410）包括存取晶体管（214,414）和非驱动器具有至少两个电阻状态的易失性电阻开关元件（212,412），其中为了在目标位单元（T）中写入新数据（T_n + 1），所述新数据取决于数据（S_n ）和源字节单元（S）之间的数据（T_n）和目标位单元（T）存储的数据（T_n）之前，行驱动器（220,420）和列驱动器（230,430）能够同时对第一行线（222,422）施加第一选择电压（V_s）以选择目标位单元（210,410），将第二选择电压（V_p-s）施加到第二行线（222'，422' ）来选择源位单元（210'，410' ）和至少一个列线（232,432）的逻辑电流（I imp），其中所述第一选择电压（V_s）高于所述第二选择电压（V_p-s），使得响应于所述电压施加到目标和源位单元，目标位单元的存取晶体管比源位单元的存取晶体管具有更低的电阻。

4. 发明公开

EP3850495A1 COMPUTER-IMPLEMENTED METHOD AND ELECTRONIC DEVICE FOR DETECTING INFLUENTIAL COMPONENTS IN A NETLIST REPRESENTING AN ELECTRICAL CIRCUIT 无效
公开(公告)号：EP3850495A1
公开(公告)日：2021-07-21
申请号：EP19768785.8
申请日：2019-09-11
申请人： Technische Universität Wien
发明人： MAHMOUDI, Hiwa , ZIMMERMANN, Horst
IPC分类号： G06F16/00

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