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1. 发明申请

US20120191887A1 COMPUTER SYSTEM AND METHOD FOR SIGNAL TRANSMITTING 审中-公开
标题翻译：计算机系统和信号传输方法
公开(公告)号：US20120191887A1
公开(公告)日：2012-07-26
申请号：US13347159
申请日：2012-01-10
申请人： TATSUYA YAMAUCHI , Masahiro Kobayashi , Ryo Yamagata , Takashi Tamura , Kenichi Watanabe
发明人： TATSUYA YAMAUCHI , Masahiro Kobayashi , Ryo Yamagata , Takashi Tamura , Kenichi Watanabe
IPC分类号： G06F13/42
CPC分类号： G06F13/4282 , G06F2213/0026
摘要： In order to suppress occurrence of a random pattern signal is suppressed without the use of a sideband signal in a long distance data transmission exceeding that defined in a PCIe interface specification, provided is a computer system, including a first component having a transmitting unit which transmits a control signal, a second component having a receiving unit which receives the control signal, a transmission path which connects the first component and the second component along which a signal is transmitted and received, wherein: in case of the transmitting unit of the first component transmits a ternary signal with three states of 0/1/Idle to the receiving unit of the second component, the transmitting unit of the first component substitutes a combination of signals representing 0/1 for a signal representing the Idle state, and transmits the substituted signals instead of the ternary signal to the receiving unit of the second component.
摘要翻译：为了抑制随机模式信号的发生，在长距离数据传输中不使用超出PCIe接口规范中规定的边带信号的情况下，提供了一种计算机系统，其包括具有发送单元的第一部件控制信号，具有接收控制信号的接收单元的第二分量，连接发送和接收信号的第一分量和第二分量的传输路径，其中：在第一分量的发送单元的情况下，将具有0/1 /空闲三种状态的三态信号发送到第二分量的接收单元，第一分量的发送单元代表表示空闲状态的信号的代表0/1的信号的组合，并且发送取代信号而不是第三组件的接收单元的三进制信号。

2. 发明授权

US06355984B2 Input-output circuit cell and semiconductor integrated circuit apparatus 失效
标题翻译：输入输出电路单元和半导体集成电路装置
公开(公告)号：US06355984B2
公开(公告)日：2002-03-12
申请号：US09828193
申请日：2001-04-09
申请人： Kazuhisa Miyamoto , Ryo Yamagata , Takayuki Uda
发明人： Kazuhisa Miyamoto , Ryo Yamagata , Takayuki Uda
IPC分类号： H01L2980
CPC分类号： H01L23/50 , H01L2224/16 , H01L2924/15174 , H01L2924/15311 , H01L2924/3011
摘要： An input-output circuit cell includes an input-output circuit formed on a semiconductor chip and having a signal terminal and an electric source terminal and a plurality of input-output bumps connected to the signal and electric-source terminals of the input-output circuit through wirings respectively, the plurality of input-output bumps being made to correspond to the input-output circuit and arranged at a center in a plane of projection of the input-output circuit. Accordingly, the input-output circuit is disposed in an arbitrary position on the semiconductor chip.
摘要翻译：输入输出电路单元包括形成在半导体芯片上并具有信号端子和电源端子的输入输出电路和连接到输入 - 输出电路的信号和电源端子的多个输入 - 输出凸块通过布线分别使多个输入输出凸块对应于输入 - 输出电路并且布置在输入 - 输出电路的投影平面中的中心。因此，输入输出电路配置在半导体芯片上的任意位置。

3. 发明授权

US5499379A Input/output execution apparatus for a plural-OS run system 失效
标题翻译：多OS运行系统的输入输出执行装置
公开(公告)号：US5499379A
公开(公告)日：1996-03-12
申请号：US8842
申请日：1993-01-25
申请人： Shunji Tanaka , Toru Ohtsuki , Hiroaki Sato , Hideo Sawamoto , Ryo Yamagata , Masaya Watanabe , Hidenori Umeno , Masatoshi Haraguchi
发明人： Shunji Tanaka , Toru Ohtsuki , Hiroaki Sato , Hideo Sawamoto , Ryo Yamagata , Masaya Watanabe , Hidenori Umeno , Masatoshi Haraguchi
IPC分类号： G06F13/10 , G06F9/318 , G06F9/455 , G06F9/46 , G06F9/48 , G06F9/00
CPC分类号： G06F9/3017 , G06F9/45558 , G06F9/4812 , G06F2009/45579
摘要： A plural-OS run system in which a plurality of operating systems (OSs) capable of operating on machines of different architectures, respectively, are allowed to run on one bare machine under the control of one control program (CP) or one control means. The input/output instruction and input/output interrupt of the operating system capable of running on a machine of the same architecture as that of the bare machine are directly executed on the bare machine without need for translation of the format. The input/output instruction and the input/output interrupt of the operating system adapted to run on a machine of the architecture differing from that of the bare machine are allowed to be directly executed while translating the format.
摘要翻译：一种多操作系统运行系统，其中可以在一个控制程序（CP）或一个控制装置的控制下，分别在不同架构的机器上操作的多个操作系统（OS）在一个裸机上运行。能够在与裸机相同架构的机器上运行的操作系统的输入/输出指令和输入/输出中断在裸机上直接执行，无需转换格式。允许在转换格式的同时直接执行适用于与裸机机架不同的架构的机器上运行的操作系统的输入/输出指令和输入/输出中断。

4. 发明授权

US5129071A Address translation apparatus in virtual machine system using a space identifier field for discriminating DATOFF (dynamic address translation off) virtual machines 失效
标题翻译：虚拟机系统中的地址转换装置，使用空间识别器字段来区分DATOFF（动态地址转换关闭）虚拟机
公开(公告)号：US5129071A
公开(公告)日：1992-07-07
申请号：US331756
申请日：1989-04-03
申请人： Ryo Yamagata , Hideo Sawamoto , Hidenori Umeno
发明人： Ryo Yamagata , Hideo Sawamoto , Hidenori Umeno
IPC分类号： G06F9/46 , G06F12/10
CPC分类号： G06F12/1036
摘要： An address translation apparatus is provided which has an address translation look-aside buffer with an entry composed of a real address field, virtual machine identifier field and space identifier field. For the translation look-aside buffer entry to be used by a general virtual machine which uses a plurality of address spaces, a virtual machine identifier for discrimination of a general virtual machine is stored in the virtual machine identifier field, and information used in discriminating an address space is stored in the space identifier field. For the translation look-aside buffer entry to be used by a dynamic address translation off (DATOFF virtual) machine which uses a single address space, an identifier commonly assigned to a group of DATOFF virtual machines is stored in the virtual machine identifier field, and a control block address used in discriminating a DATOFF virtual machine is stored in the space identifier field.
摘要翻译：提供了一种地址转换装置，其具有地址转换后备缓冲器，其具有由实际地址字段，虚拟机标识符字段和空格标识符字段组成的条目。对于由使用多个地址空间的通用虚拟机使用的翻译后备缓冲器条目，用于识别一般虚拟机的虚拟机标识符存储在虚拟机标识符字段中，并且用于区分地址空间存储在空间标识符字段中。对于使用单个地址空间的动态地址转换（DATOFF virtual）机器使用的翻译后备缓冲器条目，通常分配给一组DATOFF虚拟机的标识符存储在虚拟机标识符字段中，并且用于区分DATOFF虚拟机的控制块地址被存储在空间标识符字段中。

5. 发明授权

US09479461B2 Computer system and method for communicating data between computers 有权
标题翻译：用于在计算机之间传送数据的计算机系统和方法
公开(公告)号：US09479461B2
公开(公告)日：2016-10-25
申请号：US14360022
申请日：2012-03-16
申请人： Shuhei Eguchi , Ryo Yamagata , Yoshiki Murakami
发明人： Shuhei Eguchi , Ryo Yamagata , Yoshiki Murakami
IPC分类号： H04L12/28 , H04L12/935 , G06F13/40
CPC分类号： H04L49/30 , G06F13/4022
摘要： In a computer on the transmission side, an NW driver, which is recognized, by the OS, as an NIC driver, stores data to be transmitted and a destination SPA into a memory, and outputs a transaction layer packet (TLP), which has been generated by a first computer, to a PCIe switch. A first NIC logic of the PCIe switch of the PCIe switch corresponding to the first computer on the transmission side adds a system port address (SPA) to the TLP transferred from the first computer, and transfers the data of the TLP to a port associated with a second NIC logic and having an address indicated by the SPA (destination SPA). The second NIC logic having received the data writes the receive data into a memory of a second computer, on the reception side, which is connected to another PCIe switch where the second NIC logic exists.
摘要翻译：在发送侧的计算机中，由OS识别为NIC驱动器的NW驱动器将要发送的数据和目的地SPA存储到存储器中，并且输出具有的交易层分组（TLP）由第一台计算机生成，到PCIe交换机。对应于传输侧第一台计算机的PCIe交换机的PCIe交换机的第一个NIC逻辑将从第一台计算机传输的TLP添加系统端口地址（SPA），并将TLP的数据传输到与第二NIC逻辑并且具有由SPA（目的地SPA）指示的地址。已经接收到数据的第二NIC逻辑将接收数据写入接收侧的第二计算机的存储器，该第二计算机连接到存在第二NIC逻辑的另一个PCIe交换机。

6. 发明授权

US07036060B2 Semiconductor integrated circuit and its analyzing method 失效
公开(公告)号：US07036060B2
公开(公告)日：2006-04-25
申请号：US10452195
申请日：2003-06-03
申请人： Michinobu Nakao , Ryo Yamagata , Kazumi Hatayama , Seiji Kobayashi , Kazunori Hikone , Kotaro Shimamura
发明人： Michinobu Nakao , Ryo Yamagata , Kazumi Hatayama , Seiji Kobayashi , Kazunori Hikone , Kotaro Shimamura
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A semiconductor integrated circuit is provided whose area overhead due to provision of test points is reduced together with the test time period. In a semiconductor integrated circuit having a plurality of observation points in a tested circuit, the plurality of observation points are divided into a preset number of groups. The semiconductor integrated circuit contains at least one compressing circuit to reduce the number of bits of a multi-bit signal and to output the result (a signal of less bits) to an observable element such as an external output element or a flip-flop with a scan function. The semiconductor integrated circuit also has at least two scan chains each of which is made up with a plurality of flip-flop circuits working as shift registers. Further, the two scan chains are interconnected with a single input terminal.

7. 发明授权

US6121687A Input-output circuit cell and semiconductor integrated circuit apparatus 失效
公开(公告)号：US6121687A
公开(公告)日：2000-09-19
申请号：US987771
申请日：1997-12-09
申请人： Kazuhisa Miyamoto , Ryo Yamagata , Takayuki Uda
发明人： Kazuhisa Miyamoto , Ryo Yamagata , Takayuki Uda
IPC分类号： H01L21/822 , H01L21/82 , H01L23/50 , H01L27/04 , H01L29/80 , H01L31/112
CPC分类号： H01L23/50 , H01L2224/16 , H01L2924/15174 , H01L2924/15311 , H01L2924/3011
摘要： An input-output circuit cell includes an input-output circuit formed on a semiconductor chip and having a signal terminal and an electric source terminal and a plurality of input-output bumps connected to the signal and electric-source terminals of the input-output circuit through wirings respectively, the plurality of input-output bumps being made to correspond to the input-output circuit and arranged at a center in a plane of projection of the input-output circuit. Accordingly, the input-output circuit is disposed in an arbitrary position on the semiconductor chip.

8. 发明授权

US09612989B2 Computer system and routing control method 有权
公开(公告)号：US09612989B2
公开(公告)日：2017-04-04
申请号：US13997539
申请日：2010-12-24
申请人： Shuhei Eguchi , Ryo Yamagata , Takashi Todaka
发明人： Shuhei Eguchi , Ryo Yamagata , Takashi Todaka
IPC分类号： G06F13/40 , H04L12/935 , G06F13/36
CPC分类号： G06F13/4022 , G06F13/36 , H04L49/30
摘要： The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination bus number having the packets is determined, and the SPA is added to the packets as a label. This SPA is used to route the packets sent between ports (internal ports) that connect switches. When the packets arrive at the external port to which the target server or device is connected, the destination bus number having packets is used to send the packets to the server or device connected to the external port.

9. 发明申请

US20140006679A1 COMPUTER SYSTEM AND ROUTING CONTROL METHOD 有权
标题翻译：计算机系统和路由控制方法
公开(公告)号：US20140006679A1
公开(公告)日：2014-01-02
申请号：US13997539
申请日：2010-12-24
申请人： Shuhei Eguchi , Ryo Yamagata , Takashi Todaka
发明人： Shuhei Eguchi , Ryo Yamagata , Takashi Todaka
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , G06F13/36 , H04L49/30
摘要： The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination bus number having the packets is determined, and the SPA is added to the packets as a label. This SPA is used to route the packets sent between ports (internal ports) that connect switches. When the packets arrive at the external port to which the target server or device is connected, the destination bus number having packets is used to send the packets to the server or device connected to the external port.
摘要翻译：本发明消除了使用PCIe交换机的路由控制中总线数量的不足。系统端口地址（SPA）与目的地总线号相关联，并分配给连接到服务器和设备的端口（外部端口）。当在外部端口接收到从服务器或设备发送的数据包时，确定与具有数据包的目标总线号码相对应的系统端口地址（SPA），并将SPA作为标签添加到数据包。此SPA用于路由连接交换机的端口（内部端口）之间发送的数据包。当分组到达目标服务器或设备连接的外部端口时，具有分组的目的地总线号码用于将数据包发送到连接到外部端口的服务器或设备。

10. 发明授权

US06321355B1 Semiconductor integrated circuit and method of testing the same 失效
标题翻译：半导体集成电路和测试方法相同
公开(公告)号：US06321355B1
公开(公告)日：2001-11-20
申请号：US09204153
申请日：1998-12-03
申请人： Kouji Izaki , Tetsuya Takahashi , Ryo Yamagata
发明人： Kouji Izaki , Tetsuya Takahashi , Ryo Yamagata
IPC分类号： G01R3128
CPC分类号： G01R31/318536
摘要： An LSI having a logic circuit and a test circuit is provided with a first register which is connected between an LSI input/output pin and the logic circuit and has a first input terminal to be outputted from the first register in accordance with a system clock signal and a second input terminal, a second register which has a first input terminal inputted with an output of the first register and a second input terminal inputted with scan-in data and an output of which is connected to the second input terminal of the first register, a selector circuit which is connected to one of the first input terminal of the second register and the second terminal of the first register and selects one of a signal relating to scan-out data and an output signal of the other register so that the selected signal is inputted to the one input terminal, and a third register which receives an output of the second register and provides the received output as scan-out data in accordance with another clock signal. An output of the third register is successively provided to another LSI input/output pin. The selector circuit includes a logic gate circuit inputted with a signal indicative of an LSI test mode and the output signal of the other register.
摘要翻译：具有逻辑电路和测试电路的LSI具有连接在LSI输入/输出引脚和逻辑电路之间的第一寄存器，并具有根据系统时钟信号从第一寄存器输出的第一输入端以及第二输入端子，第二寄存器，其具有输入了第一寄存器的输出的第一输入端子和输入了扫描数据的第二输入端子，其输出端连接到第一寄存器的第二输入端子选择器电路，其连接到第二寄存器的第一输入端和第一寄存器的第二端之一，并选择与扫描输出数据有关的信号和另一寄存器的输出信号之一，使得所选择的信号被输入到一个输入端，以及第三寄存器，其接收第二寄存器的输出，并根据另一个时钟信号将接收到的输出提供为扫描数据 l。第三寄存器的输出依次提供给另一个LSI输入/输出引脚。选择器电路包括输入了指示LSI测试模式的信号和另一个寄存器的输出信号的逻辑门电路。

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