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1. 发明授权

US09478623B2 Metal gate structure 有权
标题翻译：金属门结构
公开(公告)号：US09478623B2
公开(公告)日：2016-10-25
申请号：US14497114
申请日：2014-09-25
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Peng-Soon Lim , Tsai-Jung Ho
IPC分类号： H01L29/49 , H01L29/423 , H01L21/28 , H01L21/8234 , H01L29/51
CPC分类号： H01L21/28114 , H01L21/28088 , H01L21/823456 , H01L27/088 , H01L29/42368 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A device comprises a metal gate structure in a trench and over a substrate, wherein the gate structure comprises a first metal sidewall in the trench, wherein the first metal sidewall becomes progressively thinner towards an upper portion of the first metal sidewall, a second metal sidewall in the trench, wherein the second metal sidewall becomes progressively thinner towards an upper portion of the second metal sidewall and a metal bottom layer on a bottom of the trench and between the first metal sidewall and the second metal sidewall.
摘要翻译：一种器件包括在沟槽中和衬底上的金属栅极结构，其中栅极结构包括沟槽中的第一金属侧壁，其中第一金属侧壁朝向第一金属侧壁的上部逐渐变薄，第二金属侧壁在所述沟槽中，其中所述第二金属侧壁朝向所述第二金属侧壁的上部逐渐变薄，以及在所述沟槽的底部上以及所述第一金属侧壁和所述第二金属侧壁之间的金属底层。

2. 发明授权

US11973027B2 Semiconductor device and methods of forming the same 有权
公开(公告)号：US11973027B2
公开(公告)日：2024-04-30
申请号：US17701702
申请日：2022-03-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Pei-Yu Chou , Jr-Hung Li , Liang-Yin Chen , Su-Hao Liu , Tze-Liang Lee , Meng-Han Chou , Kuo-Ju Chen , Huicheng Chang , Tsai-Jung Ho , Tzu-Yang Ho
IPC分类号： H01L23/522 , H01L21/02 , H01L21/3105 , H01L21/768 , H01L23/532 , H01L29/08 , H01L29/66 , H01L29/78 , H01L23/528 , H01L29/06
CPC分类号： H01L23/5226 , H01L21/02636 , H01L21/31053 , H01L21/76802 , H01L21/76819 , H01L21/7682 , H01L21/76843 , H01L21/76877 , H01L23/5329 , H01L29/0847 , H01L29/6656 , H01L29/66795 , H01L29/7848 , H01L29/7851 , H01L23/5283 , H01L29/0649 , H01L29/66545 , H01L29/785
摘要： A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

3. 发明公开

US20230290674A1 Dielectric Layers Having Nitrogen-Containing Crusted Surfaces 审中-公开
公开(公告)号：US20230290674A1
公开(公告)日：2023-09-14
申请号：US17833395
申请日：2022-06-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsai-Jung Ho , Po-Cheng Shih , Tze-Liang Lee
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76802 , H01L21/76826 , H01L21/76879 , H01L23/5226 , H01L21/76831 , H01L21/76897
摘要： Interconnect structures having dielectric layers with nitrogen-containing crusts and methods of fabrication thereof are disclosed herein. An exemplary method includes forming a first interconnect opening in a first interlayer dielectric (ILD) layer that exposes an underlying conductive feature, such as a source/drain, a gate, a contact, a via, or a conductive line. The method includes nitridizing sidewalls of the first interconnect opening, which are formed by the first ILD layer, before forming a first metal contact in the first interconnect opening. The nitridizing converts a portion of the first ILD layer into a nitrogen-containing crust. The first metal contact can include a metal plug and dielectric spacers between the metal plug and the nitrogen-containing crust of the first ILD layer. The method can include forming a second interconnect opening in a second ILD layer that exposes the first metal contact and forming a second metal contact in the second interconnect opening.

4. 发明申请

US20170288031A1 SELF ALIGNED CONTACT SCHEME 审中-公开
公开(公告)号：US20170288031A1
公开(公告)日：2017-10-05
申请号：US15407112
申请日：2017-01-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsai-Jung Ho , Kuang-Yuan Hsu , Pei-Ren Jeng
IPC分类号： H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L29/41783 , H01L21/76834 , H01L21/76897 , H01L21/823475 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/78
摘要： An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.

5. 发明公开

US20240274527A1 METHODS OF FORMING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20240274527A1
公开(公告)日：2024-08-15
申请号：US18616191
申请日：2024-03-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Pei-Yu Chou , Jr-Hung Li , Liang-Yin Chen , Su-Hao Liu , Tze-Liang Lee , Meng-Han Chou , Kuo-Ju Chen , Huicheng Chang , Tsai-Jung Ho , Tzu-Yang Ho
IPC分类号： H01L23/522 , H01L21/02 , H01L21/3105 , H01L21/768 , H01L23/528 , H01L23/532 , H01L29/06 , H01L29/08 , H01L29/66 , H01L29/78
CPC分类号： H01L23/5226 , H01L21/02636 , H01L21/31053 , H01L21/76802 , H01L21/76819 , H01L21/7682 , H01L21/76843 , H01L21/76877 , H01L23/5329 , H01L29/0847 , H01L29/6656 , H01L29/66795 , H01L29/7848 , H01L29/7851 , H01L23/5283 , H01L29/0649 , H01L29/66545 , H01L29/785
摘要： A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

6. 发明授权

US11842930B2 Gap patterning for metal-to-source/drain plugs in a semiconductor device 有权
公开(公告)号：US11842930B2
公开(公告)日：2023-12-12
申请号：US17662752
申请日：2022-05-10
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Lien Huang , Ching-Feng Fu , Huan-Just Lin , Fu-Sheng Li , Tsai-Jung Ho , Bor Chiuan Hsieh , Guan-Xuan Chen , Guan-Ren Wang
IPC分类号： H01L21/8234 , H01L21/768 , H01L23/535 , H01L27/088 , H01L29/08 , H01L29/417 , H01L29/66 , H01L29/06 , H01L29/78
CPC分类号： H01L21/823475 , H01L21/7684 , H01L21/76805 , H01L21/76837 , H01L21/76895 , H01L21/823418 , H01L21/823431 , H01L23/535 , H01L27/0886 , H01L29/0847 , H01L29/41791
摘要： A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

7. 发明公开

US20230282751A1 BOTTOM DIELECTRIC ISOLATION AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS 审中-公开
公开(公告)号：US20230282751A1
公开(公告)日：2023-09-07
申请号：US17833440
申请日：2022-06-06
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chia-Cheng Chen , Yun Chen Teng , Liang-Yin Chen , Yee-Chia Yeo , Tsai-Jung Ho
IPC分类号： H01L29/786 , H01L29/06 , H01L29/423 , H01L29/775 , H01L21/02 , H01L29/66
CPC分类号： H01L29/78618 , H01L29/0673 , H01L29/42392 , H01L29/78696 , H01L29/775 , H01L21/02603 , H01L21/02532 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/66439
摘要： A semiconductor structure includes a substrate and a stacked structure including channel layers interleaved with a metal gate structure. The semiconductor structure also includes an isolation feature disposed between the stacked structure and the substrate, where a bottommost portion of the metal gate structure directly contacts the isolation feature. The semiconductor structure further includes a source/drain feature disposed adjacent the stacked structure and an inner spacer disposed between the metal gate structure and the source/drain feature.

8. 发明申请

US20170040173A1 Metal Gate Structure 审中-公开
标题翻译：金属门结构
公开(公告)号：US20170040173A1
公开(公告)日：2017-02-09
申请号：US15296453
申请日：2016-10-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Peng-Soon Lim , Tsai-Jung Ho
IPC分类号： H01L21/28 , H01L21/8234 , H01L27/088 , H01L29/423
CPC分类号： H01L21/28114 , H01L21/28088 , H01L21/823456 , H01L27/088 , H01L29/42368 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A method comprises depositing a dielectric layer on sidewalls and a bottom of a trench of a gate structure, depositing a metal layer on the dielectric layer, depositing a protection layer on the metal layer, wherein an upper portion of a sidewall portion of the protection layer is thinner than a lower portion of the sidewall portion of the protection layer and etching back the metal wherein an upper portion of a first metal sidewall of the metal layer is thinner than a lower portion of the first metal sidewall and an upper portion of a second metal sidewall of the metal layer is thinner than a lower portion of the second metal sidewall.
摘要翻译：一种方法包括在栅极结构的沟槽的侧壁和底部上沉积电介质层，在电介质层上沉积金属层，在金属层上沉积保护层，其中保护层的侧壁部分的上部比所述保护层的侧壁部分的下部薄，并且蚀刻所述金属，其中所述金属层的第一金属侧壁的上部比所述第一金属侧壁的下部更薄，并且所述第二金属侧壁的上部金属层的金属侧壁比第二金属侧壁的下部薄。

9. 发明授权

US09548366B1 Self aligned contact scheme 有权
标题翻译：自对准接触方案
公开(公告)号：US09548366B1
公开(公告)日：2017-01-17
申请号：US15090341
申请日：2016-04-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsai-Jung Ho , Kuang-Yuan Hsu , Pei-Ren Jeng
IPC分类号： H01L21/768 , H01L29/417 , H01L29/78 , H01L29/66 , H01L21/8234
CPC分类号： H01L29/41783 , H01L21/76834 , H01L21/76897 , H01L21/823475 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/78
摘要： An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.
摘要翻译：一个实施例是一种方法，包括在衬底上形成第一栅极，第一栅极在相对的侧壁上具有第一栅极间隔物，在第一栅极上形成第一硬掩模层，在第一硬掩模层上形成第二硬掩模层，第二硬掩模层具有与第一硬掩模层不同的材料组成，形成与第一栅极相邻和超过第一栅极的第一介电层，蚀刻通过第一介电层的第一开口以暴露基板的一部分，至少部分所述第二硬掩模层被暴露在所述第一开口中，用导电材料填充所述第一开口，以及移除所述第二硬掩模层以及所述第一硬掩模层上方的所述导电材料和所述第一介电层的部分，以形成第一导电在剩余的第一电介质层中接触。

10. 发明公开

US20240363722A1 AIR SPACER FORMATION WITH A SPIN-ON DIELECTRIC MATERIAL 审中-公开
公开(公告)号：US20240363722A1
公开(公告)日：2024-10-31
申请号：US18769246
申请日：2024-07-10
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ting-Ting CHEN , Tsai-Jung Ho , Tsung-Han Ko , Tetsuji Ueno , Yahru Cheng , Chen-Han Wang , Keng-Chu Lin , Shuen-Shin Liang , Tsu-Hsiu Perng
IPC分类号： H01L29/49 , H01L29/06 , H01L29/66
CPC分类号： H01L29/4991 , H01L29/0653 , H01L29/6656
摘要： The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.

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