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1. 发明授权

US08759938B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08759938B2
公开(公告)日：2014-06-24
申请号：US13685019
申请日：2012-11-26
申请人： Syotaro Ono , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
发明人： Syotaro Ono , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
IPC分类号： H01L23/58
CPC分类号： H01L23/552 , H01L23/58 , H01L23/60 , H01L29/0634 , H01L29/0684 , H01L29/0696 , H01L29/1095 , H01L29/404 , H01L29/405 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a superjunction structure. The influence of external charge on device performance is suppressed using a shield electrode, field plate electrodes, and cover electrodes in various configurations. Optional embodiments include placing an interconnection film between certain electrodes and the upper surface of the superjunction structure. Cover electrodes may also be connected to various potentials to limit the effects of external charge on device performance.
摘要翻译：半导体器件包括超结构结构。使用各种结构的屏蔽电极，场板电极和覆盖电极来抑制外部电荷对器件性能的影响。可选实施例包括将互连膜放置在某些电极和超结构结构的上表面之间。覆盖电极也可以连接到各种电位以限制外部电荷对器件性能的影响。

2. 发明申请

US20130334597A1 POWER SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20130334597A1
公开(公告)日：2013-12-19
申请号：US13720344
申请日：2012-12-19
申请人： Hiroaki Yamashita , Masaru Izumisawa , Syotaro Ono , Hiroshi Ohta
发明人： Hiroaki Yamashita , Masaru Izumisawa , Syotaro Ono , Hiroshi Ohta
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0856 , H01L29/086 , H01L29/0878 , H01L29/1033 , H01L29/1095 , H01L29/4236 , H01L29/42376 , H01L29/66333 , H01L29/66348 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7802
摘要： A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type having an effective impurity concentration that is less than an effective impurity concentration of the first semiconductor layer arranged on the first semiconductor layer, a third semiconductor layer of a second conductivity type arranged on the second semiconductor layer, and a gate electrode formed in the first second semiconductor layer and the third semiconductor layer, wherein at least two regions are formed in the power semiconductor device, and a threshold voltage of the first region is different from a threshold voltage of the second region.

3. 发明授权

US08716789B2 Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US08716789B2
公开(公告)日：2014-05-06
申请号：US13610532
申请日：2012-09-11
申请人： Syotaro Ono , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
发明人： Syotaro Ono , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
IPC分类号： H01L29/66
CPC分类号： H01L29/407 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/66712 , H01L29/7395 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.
摘要翻译：根据实施例的功率半导体器件包括其中设置MOSFET元件的元件部分和设置在元件部分周围的端接部分，并且在半导体衬底中分别彼此平行地设置有柱层。该装置包括第一沟槽和第一绝缘膜。第一沟槽设置在从MOSFET元件的源电极露出的终端部分的半导体衬底中的柱层的端部之间。第一绝缘膜设置在第一沟槽的侧表面和底表面上。

4. 发明申请

US20130341751A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130341751A1
公开(公告)日：2013-12-26
申请号：US13685019
申请日：2012-11-26
申请人： Syotaro ONO , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
发明人： Syotaro ONO , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
IPC分类号： H01L23/58
CPC分类号： H01L23/552 , H01L23/58 , H01L23/60 , H01L29/0634 , H01L29/0684 , H01L29/0696 , H01L29/1095 , H01L29/404 , H01L29/405 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a superjunction structure. The influence of external charge on device performance is suppressed using a shield electrode, field plate electrodes, and cover electrodes in various configurations. Optional embodiments include placing an interconnection film between certain electrodes and the upper surface of the superjunction structure. Cover electrodes may also be connected to various potentials to limit the effects of external charge on device performance.
摘要翻译：半导体器件包括超结构结构。使用各种结构的屏蔽电极，场板电极和覆盖电极来抑制外部电荷对器件性能的影响。可选实施例包括将互连膜放置在某些电极和超结构结构的上表面之间。覆盖电极也可以连接到各种电位以限制外部电荷对器件性能的影响。

5. 发明申请

US20130248979A1 POWER SEMICONDUCTOR DEVICE 失效
标题翻译：功率半导体器件
公开(公告)号：US20130248979A1
公开(公告)日：2013-09-26
申请号：US13610532
申请日：2012-09-11
申请人： Syotaro Ono , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
发明人： Syotaro Ono , Masaru Izumisawa , Hiroshi Ohta , Hiroaki Yamashita
IPC分类号： H01L27/088
CPC分类号： H01L29/407 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/66712 , H01L29/7395 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.
摘要翻译：根据实施例的功率半导体器件包括其中设置MOSFET元件的元件部分和设置在元件部分周围的端接部分，并且在半导体衬底中分别彼此平行地设置有柱层。该器件包括第一沟槽和第一绝缘膜。第一沟槽设置在从MOSFET元件的源电极露出的终端部分的半导体衬底中的柱层的端部之间。第一绝缘膜设置在第一沟槽的侧表面和底表面上。

6. 发明授权

US08283720B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08283720B2
公开(公告)日：2012-10-09
申请号：US12050415
申请日：2008-03-18
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
IPC分类号： H01L29/00 , H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095
摘要： A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode.
摘要翻译：功率半导体器件包括：第一半导体层; 第二半导体层和第三半导体层，设置在所述第一半导体层的上部并且交替地平行于所述第一半导体层的上表面布置; 设置在所述第三半导体层上的多个第四半导体层; 选择性地形成在每个第四半导体层的上表面中的第五半导体层; 控制电极; 栅极绝缘膜; 设置在所述第一半导体层的下表面上的第一主电极; 以及设置在第四和第五半导体层上的第二主电极。第二半导体层中的杂质量和第二半导体层的第二主电极侧端部的第三半导体层中的杂质量的和小于第二半导体层的第二主电极侧的和第二半导体层和第三半导体层在从第一主电极到第二主电极的方向上。

7. 发明授权

US07989910B2 Semiconductor device including a resurf region with forward tapered teeth 有权
标题翻译：半导体装置包括具有前锥形齿的复原区域
公开(公告)号：US07989910B2
公开(公告)日：2011-08-02
申请号：US12252872
申请日：2008-10-16
申请人： Wataru Saito , Syotaro Ono , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Nana Hatano
发明人： Wataru Saito , Syotaro Ono , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Nana Hatano
IPC分类号： H01L29/66
CPC分类号： H01L29/0634 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/7811
摘要： A semiconductor device includes an n+ type semiconductor substrate 1 and a super junction region that has, on the top of the substrate 1, an n and p type pillar regions 2 and 3 provided alternately. The device also includes, in the top surface of the super junction region, a p type base region 4 and an n type source layer 5. The device also includes a gate electrode 7 on the region 4 and layer 5 via a gate-insulating film 6, a drain electrode 9 on the bottom of the substrate 1, and a source electrode 8 on the top of the substrate 1. In the top surface of the super junction region in the terminal region, a RESURF region 10 is formed. The RESURF region has a comb-like planar shape with repeatedly-formed teeth having tips facing the end portion of the terminal region.
摘要翻译：半导体器件包括n +型半导体衬底1和超结区，其在衬底1的顶部上交替设置n和p型柱状区域2,3。该器件还在超结区域的顶表面中包括ap型基极区域4和n型源极层5.该器件还包括位于区域4上的栅电极7和通过栅极绝缘膜6的层5 ，基板1底部的漏电极9以及基板1顶部的源极8.在端子区域的超结区域的上表面形成有RESURF区域10。 RESURF区域具有梳状平面形状，具有重复形成的齿，其尖端面向终端区域的端部。

8. 发明授权

US07919824B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07919824B2
公开(公告)日：2011-04-05
申请号：US12403881
申请日：2009-03-13
申请人： Syotaro Ono , Wataru Saito , Nana Hatano , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Miho Watanabe
发明人： Syotaro Ono , Wataru Saito , Nana Hatano , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Miho Watanabe
IPC分类号： H01L27/088
CPC分类号： H01L29/66712 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/7395 , H01L29/7811
摘要： A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part.
摘要翻译：半导体器件包括具有交替设置在半导体衬底上的第一导电型第一半导体柱区域和第二导电型第二半导体柱区域的超结区域。终端区域中的第一半导体柱区域和第二半导体柱区域具有由半导体衬底的顶表面上的第一半导体柱区域和第二半导体柱区域的交替层叠形成的叠层形式。终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域显示杂质浓度分布，使得多个杂质浓度峰值周期性出现。终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域具有使得随着角部更靠近圆周而变小的杂质量。

9. 发明授权

US07737469B2 Semiconductor device having superjunction structure formed of p-type and n-type pillar regions 失效
标题翻译：具有由p型和n型柱状区域形成的超结构结构的半导体装置
公开(公告)号：US07737469B2
公开(公告)日：2010-06-15
申请号：US11748869
申请日：2007-05-15
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/74
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/7395 , H01L29/7397 , H01L29/7722 , H01L29/7806 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。高电阻半导体层的掺杂浓度低于第一半导体柱区域。边界区域设置在设备中心区域和边缘终端部分之间。边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

10. 发明申请

US20080290403A1 SEMICONDUCTOR APPARATUS 失效
公开(公告)号：US20080290403A1
公开(公告)日：2008-11-27
申请号：US12123072
申请日：2008-05-19
申请人： Syotaro ONO , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Syotaro ONO , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/7395 , H01L29/861 , H01L29/868 , H01L29/872
摘要： A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.
摘要翻译：半导体装置包括第一半导体层，设置在第一半导体层的主表面上的第二半导体层，设置在主表面上并与第二半导体层相邻的第三半导体层，设置在主体上的端接半导体层在器件区域外的终端区域中的第一半导体层的表面，沟道阻挡层和沟道停止电极。沟道阻挡层设置成与终端半导体层外部的最外周部分中的第一半导体层的主表面上的端接半导体层接触，并且具有比端接半导体层更高的杂质浓度。通道阻挡电极设置在通道阻挡层的表面的至少一部分上，并且朝向端子半导体层突出超过通道阻挡层的至少表面部分。

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