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1. 发明授权

US08999766B2 ESD/antenna diodes for through-silicon vias 有权
标题翻译：用于穿硅通孔的ESD /天线二极管
公开(公告)号：US08999766B2
公开(公告)日：2015-04-07
申请号：US14133369
申请日：2013-12-18
申请人： Synopsys, Inc.
发明人： Qing Su , Min Ni , Zongwu Tang , Jamil Kawa , James D. Sproch
IPC分类号： H01L21/82 , G06F17/50 , H01L27/02 , H01L23/48 , H01L23/60 , H01L23/62
CPC分类号： G06F17/5068 , H01L23/481 , H01L23/60 , H01L23/62 , H01L27/0207 , H01L27/0255 , H01L2225/06541 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.
摘要翻译：粗略地描述，天线二极管至少部分地形成在TSV周围的排阻区内，并且通过金属1层导体连接到TSV，同时TSV连接到栅极多晶硅或扩散层放置在排除区外的一个或多个晶体管的区域。

2. 发明授权

US11651131B2 Glitch source identification and ranking 有权
公开(公告)号：US11651131B2
公开(公告)日：2023-05-16
申请号：US17335976
申请日：2021-06-01
申请人： Synopsys, Inc.
发明人： Vaibhav Jain , Solaiman Rahim , Myunghoon Yoon , Qing Su
IPC分类号： G06F30/3312 , G06F119/06 , G06F119/12
CPC分类号： G06F30/3312 , G06F2119/06 , G06F2119/12
摘要： Glitch source identification and ranking is provided by: identifying a plurality of glitch sources in a circuit layout; back referencing the plurality of glitch sources to corresponding lines in a Resistor Transistor Logic (RTL) file defining the plurality of glitch sources; identifying, in the circuit layout, a plurality of glitch terminuses associated with the plurality of glitch sources; determining a plurality of glitch power consumption values associated with the plurality of glitch sources based on fanouts in the circuit layout extending from the plurality of glitch sources to the plurality of glitch terminuses; ranking, by a processor, the plurality of glitch sources based on corresponding glitch power consumption values of the plurality of glitch power consumption values corresponding to individual glitch sources of the plurality of glitch sources; and reporting the corresponding lines in the RTL file associated with the ranked plurality of glitch sources.

3. 发明申请

US20130263076A1 BANDED COMPUTATION ARCHITECTURES 有权
标题翻译：带式计算架构
公开(公告)号：US20130263076A1
公开(公告)日：2013-10-03
申请号：US13908937
申请日：2013-06-03
申请人： Synopsys, Inc.
发明人： Min Ni , Zongwu Tang , Qing Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/50 , G06F2217/68
摘要： A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set, called a stride, into space available in shared memory given the size of the layout data specifying the sector. A plurality of threads is executed concurrently using the layout data for the sector and the currently loaded part of the basis data set. The iteration for the loading basis data set proceeds through the entire data set until the convolution operation is completed.
摘要翻译：内核在多核处理器系统中的布局的卷积包括识别包括多个评估点的布局的称为动态带的扇区。指定布局扇区的布局数据被加载到由多个处理器核共享的共享存储器中。执行内核和扇区中评估点的卷积运算。卷积操作包括在给定指定扇区的布局数据的大小的情况下，将称为步幅的基础数据集的部分迭代地加载到共享存储器中可用的空间中。使用用于扇区的布局数据和基础数据集的当前加载的部分来同时执行多个线程。加载基础数据集的迭代通过整个数据集进行，直到卷积操作完成。

4. 发明授权

US12001768B1 Enhanced glitch estimation in vectorless power analysis 有权
公开(公告)号：US12001768B1
公开(公告)日：2024-06-04
申请号：US17411578
申请日：2021-08-25
申请人： Synopsys, Inc.
发明人： Qing Su , Pankaj Singla , Solaiman Rahim , Eduard Petrus Huijbregts , Stephan Houben
IPC分类号： G06F30/3312 , G06F30/3315 , G06F119/12
CPC分类号： G06F30/3312 , G06F30/3315 , G06F2119/12
摘要： A method includes acquiring timing analysis data associated with a cell and activity data of one or more inputs of the cell, determining a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs of the cell and the timing analysis data, and estimating a glitch power based on at least the glitch toggle rate.

5. 发明授权

US11531797B1 Vector generation for maximum instantaneous peak power 有权
公开(公告)号：US11531797B1
公开(公告)日：2022-12-20
申请号：US17233126
申请日：2021-04-16
申请人： Synopsys, Inc.
发明人： Youxin Gao , Qing Su , Mayur Bubna
IPC分类号： G06F30/3312 , G06F119/12
摘要： A system and method for performing operating state analysis of an integrated circuit (IC) design is disclosed. The method includes simulating a switching operation from a first operating state to a second operating state for one or more cells of the IC design using a plurality of vectors corresponding to one or more user-specified constraints. The method include generating a time-based waveform for each cell of the one or more cells changing an operating state from the first operating state to the second operating state, and based on the generated time-based waveform, identifying one or more operating state changes corresponding to the operating state analysis and associated timing window and cell information. The method includes verifying the one or more operating state changes by the each cell of the one or more cells of the IC design meet the one or more user-specified constraints for generating an analysis report.

6. 发明授权

US08762918B2 Banded computation architectures 有权
标题翻译：带状计算架构
公开(公告)号：US08762918B2
公开(公告)日：2014-06-24
申请号：US13908937
申请日：2013-06-03
申请人： Synopsys, Inc.
发明人： Min Ni , Zongwu Tang , Qing Su
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5072 , G06F17/50 , G06F2217/68
摘要： A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set, called a stride, into space available in shared memory given the size of the layout data specifying the sector. A plurality of threads is executed concurrently using the layout data for the sector and the currently loaded part of the basis data set. The iteration for the loading basis data set proceeds through the entire data set until the convolution operation is completed.
摘要翻译：内核在多核处理器系统中的布局的卷积包括识别包括多个评估点的布局的称为动态带的扇区。指定布局扇区的布局数据被加载到由多个处理器核共享的共享存储器中。执行内核和扇区中评估点的卷积运算。卷积操作包括在给定指定扇区的布局数据的大小的情况下，将称为步幅的基础数据集的部分迭代地加载到共享存储器中可用的空间中。使用用于扇区的布局数据和基础数据集的当前加载的部分来同时执行多个线程。加载基础数据集的迭代通过整个数据集进行，直到卷积操作完成。

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