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1. 发明申请

US20140157216A1 MANAGING MODEL CHECKS OF SEQUENTIAL DESIGNS 有权
标题翻译：管理连续设计的模型检查
公开(公告)号：US20140157216A1
公开(公告)日：2014-06-05
申请号：US13691789
申请日：2012-12-01
申请人： SYNOPSYS INC.
发明人： Manish Pandey , Jinqing Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system or computer usable program product for model checking a first circuit model including determining whether the first circuit model is functionally equivalent to one of a set of prior circuit models stored in persistent memory, and in response to determining functional equivalence, utilizing a processor to provide test results for the functionally equivalent prior circuit model.
摘要翻译：一种用于模型检查第一电路模型的方法，系统或计算机可用程序产品，包括确定第一电路模型是否在功能上等同于存储在持久存储器中的一组先前电路模型中，并且响应于确定功能等同性，利用处理器为功能等效的先前电路模型提供测试结果。

2. 发明申请

US20160125111A1 MANAGING MODEL CHECKS OF SEQUENTIAL DESIGNS 审中-公开
标题翻译：管理连续设计的模型检查
公开(公告)号：US20160125111A1
公开(公告)日：2016-05-05
申请号：US14994117
申请日：2016-01-12
申请人： Synopsys Inc.
发明人： Jinqing Yu , Manish Pandey
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/504
摘要： A method, system or computer usable program product for model checking a first circuit model including receiving a request from a user for a model check of the first circuit model; responsive to receiving the user request, simulating the first circuit model to generate simulation results; hashing the first circuit model simulation results to generate a hash index; comparing the hash index to a database of prior hash indices generated from hashed simulation results of prior circuit models to determine whether the first circuit model hash index matches a prior hash index of any of the prior circuit models to identify a matching prior circuit model; upon a positive match, determining whether the first circuit model is equivalent to the matching prior circuit model; and upon a positive determination of equivalence, providing prior test results of the matching prior circuit model to the user.
摘要翻译：一种用于模型检查第一电路模型的方法，系统或计算机可用程序产品，包括从用户接收对第一电路模型的模型检查的请求; 响应于接收到用户请求，模拟第一电路模型以产生模拟结果; 散列第一个电路模型仿真结果生成散列索引; 将哈希索引与由先前的电路模型的散列模拟结果生成的先前散列索引的数据库进行比较，以确定第一电路模型散列索引是否与任何现有电路模型的先前哈希索引匹配以识别匹配的先前电路模型; 确定第一电路模型是否等于匹配的先前电路模型; 并且通过肯定的等效确定，将匹配的先前电路模型的先前测试结果提供给用户。

3. 发明授权

US10503853B1 Formal verification using cached search path information to verify previously proved/disproved properties 有权
公开(公告)号：US10503853B1
公开(公告)日：2019-12-10
申请号：US16048063
申请日：2018-07-27
申请人： Synopsys, Inc.
发明人： Arunava Saha , Himanshu Jain , Manish Pandey , Ashvin Dsouza , Per Mattias Bjesse
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504 , G06F17/5045
摘要： A formal verification tool that verifies multiple sequentially-generated versions of a core circuit design by obtaining search path information from the formal verification solver for each property that is proven or disproven during a first formal verification session involving an earlier-generated circuit design version, and utilizing the search path information to perform search-path verification processes during a subsequent formal verification session to quickly verify the proven/disproven properties in a later-generated circuit design version. Each property's search path information includes counterexample traces or proof artifacts identifying the search operations utilized to achieve a corresponding counterexample or proof object that proves/disproves the property. Search-path verification involves applying the stored search path information to the later-generated circuit design version, and determining if the same counterexample or proof object is achieved. The stored search path information is also utilized to perform efficient path-influenced search processes when the search-path verification process fails.

4. 发明授权

US10140403B2 Managing model checks of sequential designs 有权
公开(公告)号：US10140403B2
公开(公告)日：2018-11-27
申请号：US14994117
申请日：2016-01-12
申请人： Synopsys Inc.
发明人： Jinqing Yu , Manish Pandey
IPC分类号： G06F17/50
摘要： A method, system or computer usable program product for model checking a first circuit model including receiving a request from a user for a model check of the first circuit model; responsive to receiving the user request, simulating the first circuit model to generate simulation results; hashing the first circuit model simulation results to generate a hash index; comparing the hash index to a database of prior hash indices generated from hashed simulation results of prior circuit models to determine whether the first circuit model hash index matches a prior hash index of any of the prior circuit models to identify a matching prior circuit model; upon a positive match, determining whether the first circuit model is equivalent to the matching prior circuit model; and upon a positive determination of equivalence, providing prior test results of the matching prior circuit model to the user.

5. 发明授权

US11501048B1 Estimating hardness of formal properties using on-the-fly machine learning 有权
公开(公告)号：US11501048B1
公开(公告)日：2022-11-15
申请号：US16034286
申请日：2018-07-12
申请人： Synopsys, Inc.
发明人： Arunava Saha , Chuan Jiang , Manish Pandey
IPC分类号： G06F30/3323 , G06N20/00 , G06F30/327
摘要： A machine learning model predicts the hardness of unsolved properties. For example, the machine learning model may predict the relative hardness of pairs of properties—i.e., which property in the pair is harder to solve. These hardness predictions may then be used to formulate a priority order for a formal verification process to attempt to solve the unsolved properties. As the formal verification process progresses, it generates results. For example, certain properties may be solved. These results are used to update a training set, which is used to further train the machine learning model. The machine learning model is trained at runtime with incremental fine-tuning as the formal verification process progresses.

6. 发明授权

US10521536B2 RTL verification using computational complexity-based property ranking and scheduling 有权
公开(公告)号：US10521536B2
公开(公告)日：2019-12-31
申请号：US15817025
申请日：2017-11-17
申请人： Synopsys, Inc.
发明人： Jinqing Yu , Manish Pandey , Ming-Ying Chung , Arunava Saha
IPC分类号： G06F17/50 , G06N99/00 , G06N20/00
摘要： A method or apparatus comprising a verification system using a processor to utilize a first set of verification engines to solve easy properties of an integrated circuit design, such as RTL, running a machine-learning algorithm for a hardness ranking analysis on a plurality of properties based on data from the first set of verification engines, and ranking the plurality of properties by a hardness of verification. The method or apparatus further to order the plurality of properties based on the hardness of verification.

7. 发明申请

US20180144071A1 RTL Verification Using Computational Complexity-Based Property Ranking and Scheduling 审中-公开
公开(公告)号：US20180144071A1
公开(公告)日：2018-05-24
申请号：US15817025
申请日：2017-11-17
申请人： Synopsys, Inc.
发明人： Jinqing Yu , Manish Pandey , Ming-Ying Chung , Arunava Saha
IPC分类号： G06F17/50 , G06N99/00
CPC分类号： G06F17/504 , G06N20/00
摘要： A method or apparatus comprising a verification system using a processor to utilize a first set of verification engines to solve easy properties of an integrated circuit design, such as RTL, and running a machine-learning algorithm for hardness ranking analysis on a plurality of properties based on data from the first set of verification engines, and ranking the plurality of properties by a hardness of verification. The method of apparatus further to order the plurality of properties based on the hardness of verification.

8. 发明授权

US09430595B2 Managing model checks of sequential designs 有权
标题翻译：管理连续设计的模型检查
公开(公告)号：US09430595B2
公开(公告)日：2016-08-30
申请号：US13691789
申请日：2012-12-01
申请人： Synopsys Inc.
发明人： Manish Pandey , Jinqing Yu
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504
摘要： A method, system or computer usable program product for model checking a first circuit model including determining whether the first circuit model is functionally equivalent to one of a set of prior circuit models stored in persistent memory, and in response to determining functional equivalence, utilizing a processor to provide test results for the functionally equivalent prior circuit model.
摘要翻译：一种用于模型检查第一电路模型的方法，系统或计算机可用程序产品，包括确定第一电路模型是否在功能上等同于存储在持久存储器中的一组先前电路模型中，并且响应于确定功能等同性，利用处理器为功能等效的先前电路模型提供测试结果。

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