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1. 发明授权

US08621412B1 Micro-regions for auto place and route optimization 有权
标题翻译：用于自动位置和路线优化的微区域
公开(公告)号：US08621412B1
公开(公告)日：2013-12-31
申请号：US13610638
申请日：2012-09-11
申请人： Suparn Vats , John H. Mylius , Karthik Rajagopal
发明人： Suparn Vats , John H. Mylius , Karthik Rajagopal
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/06
摘要： Techniques are disclosed for partitioning a placement of a circuit design into a plurality of regions. A constraint is generated based on the partitioning of the placement and on the sequential elements that are located within each region. The constraint is provided to one or more design tools, and the constraint forces sequential elements to fall within the same region on the next placement. Some regions can be classified as guides, and these regions act as a recommendation for a design tool instead of as an explicit rule. Other regions can be classified as inclusive, and sequential elements can be allowed to enter the region but any sequential elements already in the region must stay in the region. Further regions can be classified as exclusive, and no sequential elements may enter or leave these regions on the next placement of the circuit design.
摘要翻译：公开了将电路设计的放置分割成多个区域的技术。基于位置的分割和位于每个区域内的顺序元素来生成约束。约束被提供给一个或多个设计工具，并且约束迫使顺序元素落在下一个放置的相同区域内。一些地区可以归类为指南，这些区域作为设计工具的建议，而不是明确的规则。其他区域可以被分类为包容性，并且顺序元素可以被允许进入该区域，但是该区域中已经存在的任何顺序元素必须停留在该区域中。其他区域可以被分类为排他性，并且没有顺序元件可以在电路设计的下一个放置中进入或离开这些区域。

2. 发明申请

US20140013085A1 LOW POWER AND HIGH PERFORMANCE PHYSICAL REGISTER FREE LIST IMPLEMENTATION FOR MICROPROCESSORS 有权
标题翻译：低功耗和高性能物理寄存器免费列表实现微处理器
公开(公告)号：US20140013085A1
公开(公告)日：2014-01-09
申请号：US13541351
申请日：2012-07-03
申请人： Suparn Vats , John H. Mylius , Abhijit Radhakrishnan
发明人： Suparn Vats , John H. Mylius , Abhijit Radhakrishnan
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/384
摘要： A system and method for reducing latency and power of register renaming. A free list in processor includes multiple banks for indicating availability of register identifiers used for register renaming. A register rename unit receives one or more destination architectural registers to rename with physical register identifiers. Responsive to determining the multiple banks within the free list are unbalanced with available physical register identifiers, one or more returning physical register identifiers are assigned to the destination architectural registers before assigning any physical register identifiers from any bank of the multiple banks with a lowest number of available physical register identifiers. A returning physical register identifier is a physical register identifier that is available again for assignment to a destination architectural register but not yet indicated in the free list as available. Each of the banks includes a single bit width decoded vector for indicating availability of given physical register identifiers.
摘要翻译：一种用于减少寄存器重命名的等待时间和功率的系统和方法。处理器中的一个空白列表包括用于指示用于寄存器重命名的寄存器标识符的可用性的多个存储单元。寄存器重命名单元接收一个或多个目的地体系结构寄存器以用物理寄存器标识符重命名。响应于确定空闲列表中的多个存储体与可用的物理寄存器标识符不平衡，一个或多个返回物理寄存器标识符被分配给目的地架构寄存器，然后从具有最低数量可用的物理寄存器标识符。返回的物理寄存器标识符是物理寄存器标识符，可以再次用于分配到目的地架构寄存器，但尚未在可用的空闲列表中指示。每个存储体包括用于指示给定物理寄存器标识符的可用性的单个位宽解码向量。

3. 发明授权

US09600289B2 Load-store dependency predictor PC hashing 有权
公开(公告)号：US09600289B2
公开(公告)日：2017-03-21
申请号：US13483268
申请日：2012-05-30
申请人： Stephan G. Meier , John H. Mylius , Gerard R. Williams, III , Suparn Vats
发明人： Stephan G. Meier , John H. Mylius , Gerard R. Williams, III , Suparn Vats
IPC分类号： G06F12/1018 , G06F12/0864 , G06F17/30 , G06F9/38 , G06F12/08 , G06F12/10
CPC分类号： G06F9/3834 , G06F9/3838 , G06F12/0864 , G06F12/1018 , G06F17/30949
摘要： Methods and processors for managing load-store dependencies in an out-of-order instruction pipeline. A load store dependency predictor includes a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes hashed values to identify load and store operations. When a load or store operation is detected, the PC and an architectural register number are used to create a hashed value that can be used to uniquely identify the operation. Then, the load store dependency predictor table is searched for any matching entries with the same hashed value.

4. 发明申请

US20130275720A1 ZERO CYCLE MOVE 有权
公开(公告)号：US20130275720A1
公开(公告)日：2013-10-17
申请号：US13447651
申请日：2012-04-16
申请人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
发明人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/30032 , G06F9/384
摘要： A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.
摘要翻译：一种用于减少数据移动操作的延迟的系统和方法。处理器内的寄存器重命名单元确定解码的移动指令是否符合零周期移动操作的资格。如果是这样，则控制逻辑将与移动指令的源操作数相关联的物理寄存器标识分配给移动指令的目的地操作数。此外，寄存器重命名单元标记给定的移动指令以防止其在处理器管线中继续进行。特定物理寄存器标识符的进一步维护可以在给定移动指令的提交期间由寄存器重命名单元完成。

5. 发明授权

US09128725B2 Load-store dependency predictor content management 有权
标题翻译：加载存储依赖性预测器内容管理
公开(公告)号：US09128725B2
公开(公告)日：2015-09-08
申请号：US13464647
申请日：2012-05-04
申请人： Stephan G. Meier , John H. Mylius , Gerard R. Williams, III , Suparn Vats
发明人： Stephan G. Meier , John H. Mylius , Gerard R. Williams, III , Suparn Vats
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3844
摘要： Methods and apparatuses for managing load-store dependencies in an out-of-order processor. A load store dependency predictor may include a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes a counter to indicate a strength of the dependency prediction. If the counter is above a threshold, a dependency is enforced for the load-store pair. If the counter is below the threshold, the dependency is not enforced for the load-store pair. When a store is dispatched, the table is searched, and any matching entries in the table are armed. If a load is dispatched, matches on an armed entry, and the counter is above the threshold, then the load will wait to issue until the corresponding store issues.
摘要翻译：用于在乱序处理器中管理加载存储依赖关系的方法和装置。加载存储依赖性预测器可以包括用于存储已被发现是依赖的并且无序执行的加载 - 存储对的条目的表。表中的每个条目包括一个指示依赖性预测强度的计数器。如果计数器高于阈值，则对于加载存储对执行依赖关系。如果计数器低于阈值，则不对加载存储对执行依赖关系。发送商店时，将搜索表格，并且表中的任何匹配条目都被布防。如果调度了一个负载，则在一个布防的条目上进行匹配，并且计数器高于阈值，则负载将等待发出，直到相应的存储发生。

6. 发明授权

US09575754B2 Zero cycle move 有权
标题翻译：零循环移动
公开(公告)号：US09575754B2
公开(公告)日：2017-02-21
申请号：US13447651
申请日：2012-04-16
申请人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
发明人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/30032 , G06F9/384
摘要： A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.
摘要翻译：一种用于减少数据移动操作的延迟的系统和方法。处理器内的寄存器重命名单元确定解码的移动指令是否符合零周期移动操作的资格。如果是这样，则控制逻辑将与移动指令的源操作数相关联的物理寄存器标识分配给移动指令的目的地操作数。此外，寄存器重命名单元标记给定的移动指令以防止其在处理器管线中继续进行。特定物理寄存器标识符的进一步维护可以在给定移动指令的提交期间由寄存器重命名单元完成。

7. 发明授权

US09354879B2 System and method for register renaming with register assignment based on an imbalance in free list banks 有权
标题翻译：基于自由列表银行不平衡的寄存器分配进行寄存器重命名的系统和方法
公开(公告)号：US09354879B2
公开(公告)日：2016-05-31
申请号：US13541351
申请日：2012-07-03
申请人： Suparn Vats , John H. Mylius , Abhijit Radhakrishnan
发明人： Suparn Vats , John H. Mylius , Abhijit Radhakrishnan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3012 , G06F9/384
摘要： A free list in processor includes multiple banks for indicating availability of register identifiers used for register renaming. A register rename unit receives one or more destination architectural registers to rename with physical register identifiers. Responsive to determining the multiple banks within the free list are unbalanced with available physical register identifiers, one or more returning physical register identifiers are assigned to the destination architectural registers before assigning any physical register identifiers from any bank of the multiple banks with a lowest number of available physical register identifiers. A returning physical register identifier is a physical register identifier that is available again for assignment to a destination architectural register but not yet indicated in the free list as available. Each of the banks includes a single bit width decoded vector for indicating availability of given physical register identifiers.
摘要翻译：处理器中的一个空白列表包括用于指示用于寄存器重命名的寄存器标识符的可用性的多个存储单元。寄存器重命名单元接收一个或多个目的地体系结构寄存器以用物理寄存器标识符重命名。响应于确定空闲列表中的多个存储体与可用的物理寄存器标识符不平衡，一个或多个返回物理寄存器标识符被分配给目的地架构寄存器，然后从具有最低数量可用的物理寄存器标识符。返回的物理寄存器标识符是物理寄存器标识符，可以再次用于分配到目的地架构寄存器，但尚未在可用的空闲列表中指示。每个存储体包括用于指示给定物理寄存器标识符的可用性的单个位宽解码向量。

8. 发明申请

US20130326198A1 LOAD-STORE DEPENDENCY PREDICTOR PC HASHING 有权
标题翻译：负载存储依赖性预测PC冲击
公开(公告)号：US20130326198A1
公开(公告)日：2013-12-05
申请号：US13483268
申请日：2012-05-30
申请人： Stephan G. Meier , John H. Mylius , Gerard R. Williams, III , Suparn Vats
发明人： Stephan G. Meier , John H. Mylius , Gerard R. Williams, III , Suparn Vats
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/3834 , G06F9/3838 , G06F12/0864 , G06F12/1018 , G06F17/30949
摘要： Methods and processors for managing load-store dependencies in an out-of-order instruction pipeline. A load store dependency predictor includes a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes hashed values to identify load and store operations. When a load or store operation is detected, the PC and an architectural register number are used to create a hashed value that can be used to uniquely identify the operation. Then, the load store dependency predictor table is searched for any matching entries with the same hashed value.
摘要翻译：用于在乱序指令流水线中管理加载存储依赖关系的方法和处理器。加载存储器依赖性预测器包括用于存储已被发现是依赖的并且无序执行的加载 - 存储对的条目的表。表中的每个条目都包含哈希值以识别加载和存储操作。当检测到加载或存储操作时，PC和体系结构寄存器号用于创建可用于唯一标识操作的散列值。然后，搜索具有相同散列值的任何匹配条目的加载存储相关性预测器表。

9. 发明申请

US20130298127A1 LOAD-STORE DEPENDENCY PREDICTOR CONTENT MANAGEMENT 有权
标题翻译：负载存储依赖性预测内容管理
公开(公告)号：US20130298127A1
公开(公告)日：2013-11-07
申请号：US13464647
申请日：2012-05-04
申请人： Stephan G. Meier , John H. Mylius , Gerard R. Williams, III , Suparn Vats
发明人： Stephan G. Meier , John H. Mylius , Gerard R. Williams, III , Suparn Vats
IPC分类号： G06F9/46
CPC分类号： G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3844
摘要： Methods and apparatuses for managing load-store dependencies in an out-of-order processor. A load store dependency predictor may include a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes a counter to indicate a strength of the dependency prediction. If the counter is above a threshold, a dependency is enforced for the load-store pair. If the counter is below the threshold, the dependency is not enforced for the load-store pair. When a store is dispatched, the table is searched, and any matching entries in the table are armed. If a load is dispatched, matches on an armed entry, and the counter is above the threshold, then the load will wait to issue until the corresponding store issues.
摘要翻译：用于在乱序处理器中管理加载存储依赖关系的方法和装置。加载存储依赖性预测器可以包括用于存储已被发现是依赖的并且无序执行的加载 - 存储对的条目的表。表中的每个条目包括一个指示依赖性预测强度的计数器。如果计数器高于阈值，则对于加载存储对执行依赖关系。如果计数器低于阈值，则不对加载存储对执行依赖关系。发送商店时，将搜索表格，并且表中的任何匹配条目都被布防。如果调度了一个负载，则在一个布防的条目上进行匹配，并且计数器高于阈值，则负载将等待发出，直到相应的存储发生。

10. 发明授权

US08555232B2 Wire routing using virtual landing pads 有权
标题翻译：使用虚拟着陆垫的电线路由
公开(公告)号：US08555232B2
公开(公告)日：2013-10-08
申请号：US13036308
申请日：2011-02-28
申请人： Suparn Vats , Gaurav Shrivastav
发明人： Suparn Vats , Gaurav Shrivastav
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Systems and methods for wire routing using virtual landing pads (VLPs) are described. In an embodiment, a method includes routing a wiring path between an output of a first circuit component and a VLP that represents an input of a second circuit component. For example, the VLP may have an area larger than the area of a physical pin of the second circuit component. The method may also include identifying a connection point on the VLP that is separated from an actual terminal of the second circuit, and completing the path between the connection point and the actual terminal. In some embodiments, the output of the first circuit component may also be represented by its own VLP. As such, systems and methods described herein may allow a circuit designer to perform routing procedures in a complex, highly integrated circuit, while reducing the circuit's overall capacitance and associated power consumption.
摘要翻译：描述使用虚拟着陆垫（VLP）进行线路布线的系统和方法。在一个实施例中，一种方法包括在第一电路部件的输出和代表第二电路部件的输入的VLP之间布线布线路径。例如，VLP可以具有比第二电路部件的物理引脚的面积大的面积。该方法还可以包括识别与第二电路的实际终端分离的VLP上的连接点，以及完成连接点和实际终端之间的路径。在一些实施例中，第一电路部件的输出也可以由其自己的VLP表示。因此，本文描述的系统和方法可以允许电路设计者在复杂的高度集成的电路中执行路由过程，同时减少电路的整体电容和相关的功率消耗。

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