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1. 发明申请

US20160336234A1 SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20160336234A1
公开(公告)日：2016-11-17
申请号：US15061200
申请日：2016-03-04
申请人： Sung-Min KIM , Sunhom Steve PAAK , Heon-Jong SHIN , Dong-Ho CHA
发明人： Sung-Min KIM , Sunhom Steve PAAK , Heon-Jong SHIN , Dong-Ho CHA
IPC分类号： H01L21/8234 , H01L21/02
CPC分类号： H01L21/823431 , H01L21/823481
摘要： Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
摘要翻译：提供了形成半导体器件的半导体器件和方法。所述方法可以包括形成翅片，在翅片的侧面上形成第一器件隔离层，形成延伸穿过第一器件隔离层的第二器件隔离层，形成穿过翅片的第一和第二栅极并形成第三器件隔离层在第一和第二个门之间。第一器件隔离层可以包括第一材料和第一深度处的最下表面。第二装置隔离层可以包括第二材料和在比第一深度大的第二深度的最下表面。第三装置隔离层可以延伸到翅片中，可以包括在比第一深度小的第三深度处的最下表面和不同于第一和第二材料的第三材料。

2. 发明申请

US20160181399A1 METHODS FOR FABRICATING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20160181399A1
公开(公告)日：2016-06-23
申请号：US14679166
申请日：2015-04-06
申请人： Hwi-Chan JUN , Heon-Jong SHIN , Jae-Ran JANG
发明人： Hwi-Chan JUN , Heon-Jong SHIN , Jae-Ran JANG
IPC分类号： H01L29/66 , H01L21/28 , H01L21/3213 , H01L21/768 , H01L29/40 , H01L21/8234
CPC分类号： H01L29/66553 , H01L21/28238 , H01L21/76816 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/0847 , H01L29/165 , H01L29/401 , H01L29/665 , H01L29/66545 , H01L29/7848
摘要： Methods of forming a semiconductor device are provided. The methods may include forming a gate structure on a substrate, forming a first sacrificial pattern and a second sacrificial pattern on opposing sides of the gate structure respectively and partially replacing the first sacrificial pattern with a first insulating pattern such that a portion of the first sacrificial pattern remains in the first insulating pattern and replacing the second sacrificial pattern with a second insulating pattern. The methods may also include replacing at least some of the portion of the first sacrificial pattern that remains in the first insulating pattern with a conductive pattern.
摘要翻译：提供了形成半导体器件的方法。所述方法可以包括在衬底上形成栅极结构，分别在栅极结构的相对侧上形成第一牺牲图案和第二牺牲图案，并用第一绝缘图案部分地替换第一牺牲图案，使得第一牺牲部分的一部分图案保持在第一绝缘图案中，并且用第二绝缘图案代替第二牺牲图案。所述方法还可以包括用导电图案来代替保留在第一绝缘图案中的第一牺牲图案的至少一部分。

3. 发明申请

US20160104678A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160104678A1
公开(公告)日：2016-04-14
申请号：US14801937
申请日：2015-07-17
申请人： Hwi-Chan JUN , Dae-Hee WEON , Heon-Jong SHIN , Yu-Sun LEE
发明人： Hwi-Chan JUN , Dae-Hee WEON , Heon-Jong SHIN , Yu-Sun LEE
IPC分类号： H01L23/535 , H01L29/423 , H01L27/088
CPC分类号： H01L23/535 , H01L21/823437 , H01L21/823475 , H01L27/0207 , H01L27/088 , H01L27/0886 , H01L29/42364 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, a first gate structure having a first end portion is formed on a substrate. A second gate structure is formed on the substrate, and has a second end portion opposite to the first end portion of the first gate structure in a diagonal direction. A cross-coupling pattern is formed between the first and second gate structure, and electrically connects the first and second gate structures to each other. A first contact plug directly contacts an upper portion of the first end portion of the first gate structure and a first upper sidewall of the cross-coupling pattern. A second contact plug directly contacts an upper portion of the second end portion of the second gate structure and a second upper sidewall of the cross-coupling pattern. In the semiconductor device, a parasitic capacitance due to the cross-coupling structure may decrease.
摘要翻译：在半导体器件中，具有第一端部的第一栅极结构形成在基板上。第二栅极结构形成在基板上，并且在对角线方向上具有与第一栅极结构的第一端部相对的第二端部。在第一和第二栅极结构之间形成交叉耦合图案，并将第一和第二栅极结构彼此电连接。第一接触插塞直接接触第一栅极结构的第一端部的上部和交叉耦合图案的第一上侧壁。第二接触插塞直接接触第二栅极结构的第二端部的上部和交叉耦合图案的第二上侧壁。在半导体器件中，由于交叉耦合结构引起的寄生电容可能降低。

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