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1. 发明申请

US20100001756A1 ARRAY SUBSTRATE HAVING INCREASED INSPECTION EFFICINCY AND DISPLAY APPARATUS HAVING THE SAME 有权
标题翻译：具有增加检查效率的显示装置和显示装置的阵列基板
公开(公告)号：US20100001756A1
公开(公告)日：2010-01-07
申请号：US12560699
申请日：2009-09-16
申请人： Sung-Man KIM , Myung-Koo HUR , Beom-Jun KIM , Seong-Young LEE
发明人： Sung-Man KIM , Myung-Koo HUR , Beom-Jun KIM , Seong-Young LEE
IPC分类号： G01R31/00
CPC分类号： G09G3/006 , G09G3/3677 , G09G2300/0408
摘要： In an array substrate and a display apparatus, a pixel part has a plurality of gate lines, a plurality of data lines, and a plurality of pixels electrically connected to the gate and data lines. A driving circuit drives the pixel part electrically connected to a first end of the gate lines. An inspection circuit is electrically connected to a second end of the gate lines, and inspects the pixel part in response to an inspection signal externally provided. Thus, positions and causes for defects of the pixel part may be accurately detected, thereby improving inspecting efficiency.
摘要翻译：在阵列基板和显示装置中，像素部分具有电连接到栅极和数据线的多条栅极线，多条数据线以及多个像素。驱动电路驱动电连接到栅极线的第一端的像素部分。检查电路电连接到栅极线的第二端，并且响应于外部提供的检查信号检查像素部分。因此，可以精确地检测像素部分的缺陷的位置和原因，从而提高检查效率。

2. 发明申请

US20080036725A1 GATE DRIVER AND DISPLAY APPARATUS HAVING THE SAME 有权
标题翻译：闸门驱动器和显示装置
公开(公告)号：US20080036725A1
公开(公告)日：2008-02-14
申请号：US11782957
申请日：2007-07-25
申请人： Hong-Woo LEE , Myung-Koo HUR , Jong-Hwan LEE , Beom Jun KIM , Sung-Man KIM
发明人： Hong-Woo LEE , Myung-Koo HUR , Jong-Hwan LEE , Beom Jun KIM , Sung-Man KIM
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2310/0267 , G09G2320/02 , G09G2330/08 , G11C19/28
摘要： A gate driver comprises a shift register that has a plurality of stages connected together and outputs a gate signal comprising a first pulse and a second pulse to a gate line. A stage includes a holding part, a pre-charging part, a pull-up part, and a pull-down part. The holding part discharges an output terminal to an off-voltage in response to a first clock signal. The pre-charging part turns off the holding part and outputs the first clock signal as the first pulse to the output terminal in response to an output signal of a previous stage. The pull-up part outputs a second clock signal as the second pulse to the output terminal in response to the output signal of the previous stage. The pull-down part discharges the first output terminal to the off-voltage in response to an output signal of a next stage.
摘要翻译：栅极驱动器包括具有连接在一起的多个级的移位寄存器，并将包括第一脉冲和第二脉冲的门信号输出到栅极线。舞台包括保持部分，预充电部分，上拉部分和下拉部分。保持部分响应于第一时钟信号将输出端子放电到截止电压。预充电部件关闭保持部件，并且响应于前一级的输出信号将第一时钟信号作为第一脉冲输出到输出端子。上拉部分响应于前一级的输出信号，将第二时钟信号作为第二脉冲输出到输出端。下拉部分响应于下一级的输出信号将第一输出端子放电到截止电压。

3. 发明申请

US20130141318A1 GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME 有权
标题翻译：闸门驱动电路和显示装置
公开(公告)号：US20130141318A1
公开(公告)日：2013-06-06
申请号：US13485243
申请日：2012-05-31
申请人： Beom-Jun KIM , Myung-Koo HUR , Bong-Jun LEE , Yeon-Kyu MOON , Myung-Sub LEE , Gyu-Tae KIM
发明人： Beom-Jun KIM , Myung-Koo HUR , Bong-Jun LEE , Yeon-Kyu MOON , Myung-Sub LEE , Gyu-Tae KIM
IPC分类号： G09G3/36 , H03K17/693
CPC分类号： G09G3/3688 , G09G3/36 , G09G3/3677 , G09G2300/0426 , G09G2310/0251 , G09G2310/0291 , G09G2310/08 , G11C19/28 , H03K17/693
摘要： A gate driving circuit is provided which includes a plurality of stages cascade-connected with each other and outputting a plurality of gate signals. An n-th (n is a natural number) stage includes a gate output part, a first node control part and a carry part. The gate output part includes a first transistor. The first transistor outputs a high voltage of a clock signal to a high voltage of an n-th gate signal in response to a high voltage of a control node. The first node control part is connected to the control node to control a signal of the control node and includes at least one transistor having a channel longer than the channel length of the first transistor. The carry part outputs the high voltage of the clock signal to an n-th carry signal in response to the signal of the control node.
摘要翻译：提供一种栅极驱动电路，其包括彼此级联的多个级并输出多个栅极信号。第n（n是自然数）级包括门输出部分，第一节点控制部分和进位部分。栅极输出部分包括第一晶体管。第一晶体管响应于控制节点的高电压而将时钟信号的高电压输出到第n栅极信号的高电压。第一节点控制部分连接到控制节点以控制控制节点的信号，并且包括至少一个具有比第一晶体管的沟道长度更长的沟道的晶体管。进位部分响应于控制节点的信号将时钟信号的高电压输出到第n进位信号。

4. 发明申请

US20080316384A1 DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY APPARATUS HAVING THE SAME 有权
标题翻译：显示基板，其制造方法和具有该基板的显示装置
公开(公告)号：US20080316384A1
公开(公告)日：2008-12-25
申请号：US12033986
申请日：2008-02-20
申请人： Bong-Jun LEE , Myung-Koo HUR , Jong-Oh KIM , Dong-Wuuk SEO , Sung-Man KIM
发明人： Bong-Jun LEE , Myung-Koo HUR , Jong-Oh KIM , Dong-Wuuk SEO , Sung-Man KIM
IPC分类号： G02F1/136 , H01L29/04 , H01L21/84
CPC分类号： G02F1/136213 , H01L27/12 , H01L27/124 , H01L29/41733
摘要： A display substrate includes a first metal pattern formed on a substrate and includes a data line to which a pixel voltage is applied, an insulating layer formed on the substrate on which the first metal pattern is formed, an active pattern formed on the insulating layer, a second metal pattern formed on the insulating layer and including a gate line and a storage line, the gate line crossing the data line, a scanning signal applied to the gate line, a protective layer formed on the substrate on which the second metal pattern is formed, and a pixel electrode formed on the protective layer. A method for manufacturing the display substrate, and a display apparatus including the display substrate are further provided.
摘要翻译：显示基板包括形成在基板上的第一金属图案，并且包括施加了像素电压的数据线，形成在其上形成有第一金属图案的基板上的绝缘层，形成在绝缘层上的有源图案，形成在绝缘层上的第二金属图案，包括栅极线和存储线，与数据线交叉的栅极线，施加到栅极线的扫描信号，形成在基板上的保护层，第二金属图案以及形成在保护层上的像素电极。还提供了一种制造显示基板的方法，以及包括显示基板的显示装置。

5. 发明申请

US20080067512A1 ARRAY SUBSTRATE AND DISPLAY APPARATUS HAVING THE SAME 有权
标题翻译：阵列基板和显示装置
公开(公告)号：US20080067512A1
公开(公告)日：2008-03-20
申请号：US11839125
申请日：2007-08-15
申请人： Bong-Jun LEE , Myung-Koo HUR , Sung-Man KIM , Hong-Woo LEE
发明人： Bong-Jun LEE , Myung-Koo HUR , Sung-Man KIM , Hong-Woo LEE
IPC分类号： H01L33/00 , G02F1/1343 , H01L29/04
CPC分类号： G09G3/3659 , G09G3/3614 , G09G2300/0443 , G09G2300/0452 , G09G2310/0251 , G09G2310/0281
摘要： In an array substrate and a display apparatus, a gate line receives a gate pulse during a present 1H period and a data line receives a pixel voltage having a polarity inverted at every frame. When a thin film transistor is turned on in response to the gate pulse during the present 1H period, a pixel electrode receives the pixel voltage through the thin film transistor during the present 1H period. A pre-charging part pre-charges the pixel electrode to a common voltage that is a reference voltage of the pixel voltage in response to a previous gate pulse during a previous 1H period
摘要翻译：在阵列基板和显示装置中，栅极线在当前1H周期期间接收栅极脉冲，并且数据线接收每帧具有极性反转的像素电压。当在本1H时段期间响应于栅极脉冲导通薄膜晶体管时，像素电极在本1H时段期间通过薄膜晶体管接收像素电压。预充电部件将像素电极预先充电到作为像素电压的参考电压的公共电压，该公共电压响应于之前的1H周期期间的先前的栅极脉冲

6. 发明申请

US20080001904A1 GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME 有权
标题翻译：闸门驱动电路和显示装置
公开(公告)号：US20080001904A1
公开(公告)日：2008-01-03
申请号：US11761149
申请日：2007-06-11
申请人： Sung-Man KIM , Myung-Koo HUR , Jong-Hwan LEE , Hong-Woo LEE
发明人： Sung-Man KIM , Myung-Koo HUR , Jong-Hwan LEE , Hong-Woo LEE
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2300/0408 , G11C19/28
摘要： A gate driving circuit includes stages connected in series. In a stage, a pull-up part pulls up a present gate signal to a level of a first clock signal, and a pull-down part receives a next gate signal from a next stage to discharge the present gate signal to an off-voltage. A pull-up driving part turns on or turns off the pull-up part and the carry part. A holding part holds the present gate signal at the off-voltage and a present inverter turns on or turns off the holding part in response to the first clock signal. A ripple preventing capacitor is connected between a present node and an output terminal of a previous stage's inverter to prevent a ripple at the present Q-node in response to an output signal from the previous inverter.
摘要翻译：栅极驱动电路包括串联连接的级。在一个阶段中，上拉部分将当前栅极信号提升到第一时钟信号的电平，并且下拉部分从下一级接收下一个栅极信号，以将当前栅极信号放电到截止电压。上拉驱动部分打开或关闭上拉部分和进位部分。保持部分将当前门信号保持在截止电压，并且本逆变器响应于第一时钟信号而导通或关断保持部分。防波电容器连接在前级逆变器的当前节点和输出端之间，以防止来自前一个逆变器的输出信号在当前Q节点处产生纹波。

7. 发明申请

US20100171123A1 DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US20100171123A1
公开(公告)日：2010-07-08
申请号：US12348790
申请日：2009-01-05
申请人： Myung-Koo HUR
发明人： Myung-Koo HUR
IPC分类号： H01L33/00 , H01L21/30
CPC分类号： H01L29/78696 , H01L27/1248 , H01L29/66765
摘要： A display apparatus includes a gate electrode, a first insulating layer pattern formed over the gate electrode, a second insulating layer pattern formed over the first insulating layer pattern, exposing a portion of the first insulating layer, a semiconductor film pattern formed over the second insulating layer pattern and over the first insulating layer pattern, an impurity-doped semiconductor film pattern formed on the semiconductor film pattern, wherein the impurity-doped semiconductor film pattern contacts the top surface of the semiconductor film pattern and exposes a portion of the semiconductor film pattern formed over the gate electrode, a source electrode and a drain electrode each formed over a portion of the impurity doped semiconductor film pattern, a protection film pattern formed over the source electrode and the drain electrode in a TFT area, the protection film pattern having a contact hole over the drain electrode, a pixel electrode pattern formed on the protection film pattern and_electrically connected to the drain electrode.
摘要翻译：一种显示装置，包括栅电极，形成在栅电极上的第一绝缘层图案，形成在第一绝缘层图案上的第二绝缘层图案，暴露第一绝缘层的一部分，形成在第二绝缘层上的半导体膜图案并且在所述第一绝缘层图案之上，形成在所述半导体膜图案上的杂质掺杂半导体膜图案，其中所述杂质掺杂半导体膜图案接触所述半导体膜图案的顶表面并且暴露所述半导体膜图案的一部分形成在所述栅电极上，源电极和漏电极，各自形成在所述杂质掺杂半导体膜图案的一部分上，在TFT区域中形成在所述源电极和所述漏极上的保护膜图案，所述保护膜图案具有漏极上的接触孔，形成在保护膜上的像素电极图案 m图案并且电连接到漏电极。

8. 发明申请

US20110140117A1 DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：显示基板及其制造方法
公开(公告)号：US20110140117A1
公开(公告)日：2011-06-16
申请号：US12956706
申请日：2010-11-30
申请人： Mi-Ae LEE , Yeo-Geon YOON , Myung-Koo HUR
发明人： Mi-Ae LEE , Yeo-Geon YOON , Myung-Koo HUR
IPC分类号： H01L51/52 , H01L51/56
CPC分类号： H01L27/12 , H01L27/124
摘要： A display substrate includes a base substrate, a signal line, a pad electrode, an organic layer, and a conductive member. The signal line is formed in a display area of the display substrate. The pad electrode extends from the signal line in a peripheral area of the display substrate. The organic layer is formed on the base substrate on which the signal line and the pad electrode are formed with a contact hole formed in correspondence with the pad electrode. The contact hole exposes a portion of the pad electrode. The conductive member includes conductive balls disposed in the contact hole and electrically connects the pad electrode with a connection terminal of a driving part providing a driving signal with the signal lines.
摘要翻译：显示基板包括基底，信号线，焊盘电极，有机层和导电部件。信号线形成在显示基板的显示区域中。焊盘电极从显示基板的周边区域中的信号线延伸。有机层形成在其上形成信号线和焊盘电极的基底基板上，具有与焊盘电极对应形成的接触孔。接触孔暴露焊盘电极的一部分。导电构件包括设置在接触孔中的导电球，并且将焊盘电极与驱动信号的连接端电连接到信号线。

9. 发明申请

US20100225842A1 LIQUID CRYSTAL DISPLAY INCLUDING STEP-DOWN CAPACITOR 审中-公开
标题翻译：液晶显示，包括降压电容
公开(公告)号：US20100225842A1
公开(公告)日：2010-09-09
申请号：US12534261
申请日：2009-08-03
申请人： Myung-Koo HUR , Cheol-Gon LEE , Yoon-Sung UM
发明人： Myung-Koo HUR , Cheol-Gon LEE , Yoon-Sung UM
IPC分类号： G02F1/1368 , G02F1/1343
CPC分类号： G02F1/13624 , G02F1/136213 , G02F2001/134345
摘要： A liquid crystal display includes; first sub-pixel electrodes and second sub-pixel electrodes, a plurality of first thin film transistors connected to the first sub-pixel electrode, a plurality of second thin film transistors connected to the second sub-pixel electrode, a plurality of third thin film transistors connected to the second sub-pixel electrode, a plurality of first gate lines connected to the first and second thin film transistors, a plurality of data lines connected to the first and second thin film transistors, a plurality of second gate lines connected to the third thin film transistors, and a capacitor electrode line including a capacitor electrode which is vertically aligned the drain electrodes of the third thin film transistors, wherein the capacitor electrode line is applied with a voltage that is less than a minimum value of a voltage applied to the data line or more than a maximum value thereof.
摘要翻译：液晶显示器包括：第一子像素电极和第二子像素电极，连接到第一子像素电极的多个第一薄膜晶体管，连接到第二子像素电极的多个第二薄膜晶体管，多个第三薄膜晶体管连接到第二子像素电极的晶体管，连接到第一和第二薄膜晶体管的多个第一栅极线，连接到第一和第二薄膜晶体管的多条数据线，连接到第二和第二薄膜晶体管的多条第二栅极线第三薄膜晶体管和包括与第三薄膜晶体管的漏电极垂直排列的电容器电极的电容器电极线，其中电容器电极线施加小于施加到第三薄膜晶体管的电压的最小值的电压数据线或大于其最大值。

10. 发明申请

US20110033991A1 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20110033991A1
公开(公告)日：2011-02-10
申请号：US12909757
申请日：2010-10-21
申请人： Myung-Koo HUR
发明人： Myung-Koo HUR
IPC分类号： H01L21/84
CPC分类号： H01L27/1248 , H01L27/1214 , H01L27/124 , H01L27/1288
摘要： A thin film transistor array panel includes a substrate, a data line and a gate electrode formed on the substrate, a insulating layer formed on the data line and the gate electrode, a semiconductor layer formed on the insulating layer, a drain electrode and a source electrode formed on the semiconductor layer, a passivation layer formed on the drain electrode and the source electrode including a first contact hole to expose a portion of the data line, a second contact hole to expose a portion of the source electrode, a third contact hole to expose a portion of the drain electrode, and a fourth contact hole to expose a portion of gate electrode, a first connector formed on the passivation layer and connected to the data line and the source electrode through the first contact hole and the second contact hole, a gate line formed on the passivation layer and connected to the gate electrode through the fourth contact hole, and a pixel electrode connected to the drain electrode through the third contact hole.
摘要翻译：薄膜晶体管阵列面板包括基板，数据线和形成在基板上的栅电极，形成在数据线和栅电极上的绝缘层，形成在绝缘层上的半导体层，漏电极和源极电极，形成在所述半导体层上，钝化层，形成在所述漏电极和所述源电极上，所述钝化层包括第一接触孔以暴露所述数据线的一部分;第二接触孔，用于暴露所述源电极的一部分;第三接触孔露出一部分漏电极和第四接触孔，以露出栅电极的一部分;形成在钝化层上并通过第一接触孔和第二接触孔连接到数据线和源电极的第一连接器形成在钝化层上并通过第四接触孔连接到栅电极的栅极线和通过t连接到漏电极的像素电极连接孔。

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