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1. 发明申请

US20110068481A1 PACKAGE-ON-PACKAGE TYPE SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：包装式封装型半导体封装及其制造方法
公开(公告)号：US20110068481A1
公开(公告)日：2011-03-24
申请号：US12872448
申请日：2010-08-31
申请人： Sung-Kyu PARK , Tae-Sung Park , Kyung-Man Kim , Hye-Jin Kim
发明人： Sung-Kyu PARK , Tae-Sung Park , Kyung-Man Kim , Hye-Jin Kim
IPC分类号： H01L23/48
CPC分类号： H01L23/3128 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/13025 , H01L2224/14181 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73207 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2225/1082 , H01L2225/1088 , H01L2225/1094 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided are a semiconductor package and a method for fabricating the same. The semiconductor package includes a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate and comprising a redistribution, and a molding layer molding the lower semiconductor chip, an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, with the upper package being stacked on the lower package. The semiconductor package further includes an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper and lower packages to each other, and a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper and lower packages to each other.
摘要翻译：提供半导体封装及其制造方法。半导体封装包括下封装，其包括下基板，安装在下基板上的下半导体芯片，并且包括再分布，以及模制下半导体芯片的模制层，上封装，包括上基板和上半导体芯片，上部衬底，其中上部封装堆叠在下部封装上。所述半导体封装还包括电连接器，所述电互连器从所述上衬底延伸到所述模制层中并且连接到所述重新分配以将所述上部和下部封装彼此电连接;以及虚设互连器，其从所述上衬底延伸到所述模制层中以物理耦合上下包装彼此。

2. 发明授权

US08399992B2 Package-on-package type semiconductor package 有权
标题翻译：封装封装型半导体封装
公开(公告)号：US08399992B2
公开(公告)日：2013-03-19
申请号：US12872448
申请日：2010-08-31
申请人： Sung-Kyu Park , Tae-Sung Park , Kyung-Man Kim , Hye-Jin Kim
发明人： Sung-Kyu Park , Tae-Sung Park , Kyung-Man Kim , Hye-Jin Kim
IPC分类号： H01L23/48
CPC分类号： H01L23/3128 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/13025 , H01L2224/14181 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73207 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2225/1082 , H01L2225/1088 , H01L2225/1094 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided are a semiconductor package and a method for fabricating the same. The semiconductor package includes a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate and comprising a redistribution, and a molding layer molding the lower semiconductor chip, an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, with the upper package being stacked on the lower package. The semiconductor package further includes an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper and lower packages to each other, and a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper and lower packages to each other.
摘要翻译：提供半导体封装及其制造方法。半导体封装包括下封装，其包括下基板，安装在下基板上的下半导体芯片，并且包括再分布，以及模制下半导体芯片的模制层，上封装，包括上基板和上半导体芯片，上部衬底，其中上部封装堆叠在下部封装上。所述半导体封装还包括电连接器，所述电互连器从所述上衬底延伸到所述模制层中并且连接到所述重新分配以将所述上部和下部封装彼此电连接;以及虚设互连器，其从所述上衬底延伸到所述模制层中以物理耦合上下包装彼此。

3. 发明申请

US20080067660A1 SEMICONDUCTOR DEVICE PACKAGE 有权
标题翻译：半导体器件封装
公开(公告)号：US20080067660A1
公开(公告)日：2008-03-20
申请号：US11855958
申请日：2007-09-14
申请人： Hye-Jin Kim , Kyung-Man Kim
发明人： Hye-Jin Kim , Kyung-Man Kim
IPC分类号： H01L23/52
CPC分类号： H01L23/3128 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/48228 , H01L2224/48471 , H01L2224/49175 , H01L2224/73265 , H01L2225/06565 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/4554
摘要： A semiconductor device package includes a semiconductor chip having bonding pads; a printed circuit board (PCB) including an insulation pattern with a groove and bonding electrodes corresponding to the bonding pads, the groove corresponding to the edge of the semiconductor chip and being formed to partially expose a lower portion of the edge of the semiconductor chip; an adhesive material provided for adhering the bottom of the semiconductor chip to the insulation pattern to mount the semiconductor chip on the PCB; bonding wires provided for electrically connecting the bonding electrodes to the corresponding bonding pads; and a molding material provided for sealing the PCB, the semiconductor chip, the adhesive material, and the bonding wires.
摘要翻译：半导体器件封装包括具有接合焊盘的半导体芯片; 包括具有凹槽的绝缘图案和与所述接合焊盘对应的接合电极的印刷电路板（PCB），所述凹槽对应于所述半导体芯片的边缘并形成为部分地暴露所述半导体芯片的边缘的下部; 提供用于将半导体芯片的底部粘附到绝缘图案以将半导体芯片安装在PCB上的粘合材料; 用于将接合电极电连接到相应的接合焊盘的接合线; 以及用于密封PCB，半导体芯片，粘合材料和接合线的成型材料。

4. 发明授权

US09496216B2 Semiconductor package including stacked semiconductor chips and a redistribution layer 有权
标题翻译：包括堆叠半导体芯片和再分配层的半导体封装
公开(公告)号：US09496216B2
公开(公告)日：2016-11-15
申请号：US13725132
申请日：2012-12-21
申请人： Sung-Hoon Chun , Hye-Jin Kim , Sang-Ho An , Kyung-Man Kim , Seok-Chan Lee
发明人： Sung-Hoon Chun , Hye-Jin Kim , Sang-Ho An , Kyung-Man Kim , Seok-Chan Lee
IPC分类号： H01L21/02 , H01L23/50 , H01L25/065 , H01L25/18 , H01L23/522 , H01L49/02 , H01L23/00 , H01L23/525
CPC分类号： H01L23/50 , H01L23/5223 , H01L23/525 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L28/40 , H01L2224/02166 , H01L2224/02375 , H01L2224/02381 , H01L2224/0401 , H01L2224/04042 , H01L2224/05548 , H01L2224/05553 , H01L2224/05554 , H01L2224/05567 , H01L2224/06102 , H01L2224/06135 , H01L2224/131 , H01L2224/16135 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/48137 , H01L2224/48145 , H01L2224/48147 , H01L2224/48195 , H01L2224/48227 , H01L2224/48463 , H01L2224/48465 , H01L2224/49109 , H01L2224/49171 , H01L2224/49175 , H01L2224/49177 , H01L2224/73207 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06562 , H01L2924/00014 , H01L2924/1431 , H01L2924/1434 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2224/05552
摘要： Semiconductor packages including stacked semiconductor chips are provided. The semiconductor packages may include first semiconductor chips and a second semiconductor chip that are stacked sequentially on a board. The semiconductor packages may also include a wiring layer on the memory chips and the wiring layer may include redistribution patterns and redistribution pads. Each of the memory chips may include a data pad. The data pads of the first semiconductor chips may be electrically connected to the board via the second semiconductor chip, some of redistribution patterns, and some of redistribution pads.
摘要翻译：提供包括堆叠半导体芯片的半导体封装。半导体封装可以包括顺序堆叠在板上的第一半导体芯片和第二半导体芯片。半导体封装还可以包括存储器芯片上的布线层，并且布线层可以包括再分配图案和再分布垫。每个存储器芯片可以包括数据焊盘。第一半导体芯片的数据焊盘可以经由第二半导体芯片电连接到板，一些再分布图案和一些再分布焊盘。

5. 发明申请

US20110095424A1 SEMICONDUCTOR PACKAGE STRUCTURE 有权
标题翻译：半导体封装结构
公开(公告)号：US20110095424A1
公开(公告)日：2011-04-28
申请号：US12855322
申请日：2010-08-12
申请人： In-Sang Song , Hye-Jin Kim , Kyung-Man Kim
发明人： In-Sang Song , Hye-Jin Kim , Kyung-Man Kim
IPC分类号： H01L23/498
CPC分类号： H01L25/105 , H01L21/568 , H01L23/481 , H01L23/49833 , H01L25/0657 , H01L2224/02377 , H01L2224/05548 , H01L2224/05568 , H01L2224/13024 , H01L2224/32145 , H01L2224/32225 , H01L2224/9205 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311
摘要： The semiconductor package structure includes first and second packages. The first package has at least one first semiconductor chip disposed on a first printed circuit board, and at least one first pad disposed on the at least one first semiconductor chip. The second package has at least one second pad disposed on the first package, and at least one second semiconductor chip disposed on the at least one second pad. The at least one first semiconductor chip is electrically connected to the first printed circuit board. The at least one second pad is electrically connected to the at least one second semiconductor chip. The at least one second pad faces the at least one first pad.
摘要翻译：半导体封装结构包括第一和第二封装。第一封装具有设置在第一印刷电路板上的至少一个第一半导体芯片和设置在至少一个第一半导体芯片上的至少一个第一焊盘。所述第二封装具有设置在所述第一封装上的至少一个第二焊盘以及设置在所述至少一个第二焊盘上的至少一个第二半导体芯片。所述至少一个第一半导体芯片电连接到所述第一印刷电路板。所述至少一个第二焊盘电连接到所述至少一个第二半导体芯片。所述至少一个第二垫面对所述至少一个第一垫。

6. 发明申请

US20130161788A1 Semiconductor Package Including Stacked Semiconductor Chips and a Redistribution Layer 有权
标题翻译：半导体封装包括堆叠半导体芯片和再分配层
公开(公告)号：US20130161788A1
公开(公告)日：2013-06-27
申请号：US13725132
申请日：2012-12-21
申请人： Sung-Hoon Chun , Hye-Jin Kim , Sang-Ho An , Kyung-Man Kim , Seok-Chan Lee
发明人： Sung-Hoon Chun , Hye-Jin Kim , Sang-Ho An , Kyung-Man Kim , Seok-Chan Lee
IPC分类号： H01L23/50
CPC分类号： H01L23/50 , H01L23/5223 , H01L23/525 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L28/40 , H01L2224/02166 , H01L2224/02375 , H01L2224/02381 , H01L2224/0401 , H01L2224/04042 , H01L2224/05548 , H01L2224/05553 , H01L2224/05554 , H01L2224/05567 , H01L2224/06102 , H01L2224/06135 , H01L2224/131 , H01L2224/16135 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/48137 , H01L2224/48145 , H01L2224/48147 , H01L2224/48195 , H01L2224/48227 , H01L2224/48463 , H01L2224/48465 , H01L2224/49109 , H01L2224/49171 , H01L2224/49175 , H01L2224/49177 , H01L2224/73207 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06562 , H01L2924/00014 , H01L2924/1431 , H01L2924/1434 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2224/05552
摘要： Semiconductor packages including stacked semiconductor chips are provided. The semiconductor packages may include first semiconductor chips and a second semiconductor chip that are stacked sequentially on a board. The semiconductor packages may also include a wiring layer on the memory chips and the wiring layer may include redistribution patterns and redistribution pads. Each of the memory chips may include a data pad. The data pads of the first semiconductor chips may be electrically connected to the board via the second semiconductor chip, some of redistribution patterns, and some of redistribution pads.
摘要翻译：提供包括堆叠半导体芯片的半导体封装。半导体封装可以包括顺序堆叠在板上的第一半导体芯片和第二半导体芯片。半导体封装还可以包括存储器芯片上的布线层，并且布线层可以包括再分配图案和再分布垫。每个存储器芯片可以包括数据焊盘。第一半导体芯片的数据焊盘可以经由第二半导体芯片电连接到板，一些再分布图案和一些再分布焊盘。

7. 发明授权

US08426956B2 Semiconductor package structure having plural packages in a stacked arrangement 有权
标题翻译：具有堆叠布置的多个封装的半导体封装结构
公开(公告)号：US08426956B2
公开(公告)日：2013-04-23
申请号：US12855322
申请日：2010-08-12
申请人： In-Sang Song , Hye-Jin Kim , Kyung-Man Kim
发明人： In-Sang Song , Hye-Jin Kim , Kyung-Man Kim
IPC分类号： H01L23/488
CPC分类号： H01L25/105 , H01L21/568 , H01L23/481 , H01L23/49833 , H01L25/0657 , H01L2224/02377 , H01L2224/05548 , H01L2224/05568 , H01L2224/13024 , H01L2224/32145 , H01L2224/32225 , H01L2224/9205 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311
摘要： The semiconductor package structure includes first and second packages. The first package has at least one first semiconductor chip disposed on a first printed circuit board, and at least one first pad disposed on the at least one first semiconductor chip. The second package has at least one second pad disposed on the first package, and at least one second semiconductor chip disposed on the at least one second pad. The at least one first semiconductor chip is electrically connected to the first printed circuit board. The at least one second pad is electrically connected to the at least one second semiconductor chip. The at least one second pad faces the at least one first pad.
摘要翻译：半导体封装结构包括第一和第二封装。第一封装具有设置在第一印刷电路板上的至少一个第一半导体芯片和设置在至少一个第一半导体芯片上的至少一个第一焊盘。所述第二封装具有设置在所述第一封装上的至少一个第二焊盘以及设置在所述至少一个第二焊盘上的至少一个第二半导体芯片。所述至少一个第一半导体芯片电连接到所述第一印刷电路板。所述至少一个第二焊盘电连接到所述至少一个第二半导体芯片。所述至少一个第二垫面对所述至少一个第一垫。

8. 发明授权

US07750453B2 Semiconductor device package with groove 有权
标题翻译：半导体器件封装带槽
公开(公告)号：US07750453B2
公开(公告)日：2010-07-06
申请号：US11855958
申请日：2007-09-14
申请人： Hye-Jin Kim , Kyung-Man Kim
发明人： Hye-Jin Kim , Kyung-Man Kim
IPC分类号： H01L23/02
CPC分类号： H01L23/3128 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/48228 , H01L2224/48471 , H01L2224/49175 , H01L2224/73265 , H01L2225/06565 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/4554
摘要： A semiconductor device package includes a semiconductor chip having bonding pads; a printed circuit board (PCB) including an insulation pattern with a groove and bonding electrodes corresponding to the bonding pads, the groove corresponding to the edge of the semiconductor chip and being formed to partially expose a lower portion of the edge of the semiconductor chip; an adhesive material provided for adhering the bottom of the semiconductor chip to the insulation pattern to mount the semiconductor chip on the PCB; bonding wires provided for electrically connecting the bonding electrodes to the corresponding bonding pads; and a molding material provided for sealing the PCB, the semiconductor chip, the adhesive material, and the bonding wires.
摘要翻译：半导体器件封装包括具有接合焊盘的半导体芯片; 包括具有凹槽的绝缘图案和与所述接合焊盘对应的接合电极的印刷电路板（PCB），所述凹槽对应于所述半导体芯片的边缘并形成为部分地暴露所述半导体芯片的边缘的下部; 提供用于将半导体芯片的底部粘附到绝缘图案以将半导体芯片安装在PCB上的粘合材料; 用于将接合电极电连接到相应的接合焊盘的接合线; 以及用于密封PCB，半导体芯片，粘合材料和接合线的成型材料。

9. 发明授权

US08736519B2 Pixel driving circuit with ground terminal voltage controller for an electro-luminance display device 有权
标题翻译：具有用于电亮度显示装置的接地端子电压控制器的像素驱动电路
公开(公告)号：US08736519B2
公开(公告)日：2014-05-27
申请号：US11819933
申请日：2007-06-29
申请人： Seung-Chan Byun , Kyung-Man Kim , Seong-Ho Baik , In-Hwan Kim
发明人： Seung-Chan Byun , Kyung-Man Kim , Seong-Ho Baik , In-Hwan Kim
IPC分类号： G09G3/30
CPC分类号： G09G3/3233 , G09G2300/0842 , G09G2310/0254 , G09G2320/0238 , G09G2320/043
摘要： An organic electro luminance display device according to the present invention comprises a plurality of gate lines and data lines to define a plurality of pixels and a plurality of power lines to apply a signal to the pixels; a data driving unit for supplying the signal to the data line; an emitting unit at each pixel to emit; a first thin film transistor at each pixel, the first thin film transistor being turned on by the signal inputted through the gate line; a second thin film transistor at each pixel, the second thin film transistor being turned on to apply the signal to the emitting signal through the power line when the first thin film transistor is turned on; a ground terminal voltage controlling unit for controlling a first ground terminal voltage and a second ground terminal voltage to determine respectively the voltage output from the data driving unit and the voltage applied to the emitting unit according to the first ground terminal voltage and the second ground terminal voltage, wherein the second ground terminal voltage is higher than the first ground terminal voltage to apply the voltage lower than a reference voltage to the second thin film transistor.
摘要翻译：根据本发明的有机电致亮度显示装置包括多个栅极线和数据线，以限定多个像素和多个电源线以向像素施加信号; 数据驱动单元，用于将信号提供给数据线; 每个像素发射的发射单元; 在每个像素处的第一薄膜晶体管，所述第一薄膜晶体管由通过所述栅极线输入的信号导通; 在每个像素处的第二薄膜晶体管，当所述第一薄膜晶体管导通时，所述第二薄膜晶体管导通，以通过所述电源线将所述信号施加到所述发射信号; 接地端子电压控制单元，用于控制第一接地端子电压和第二接地端子电压，以分别根据第一接地端子电压和第二接地端子确定从数据驱动单元输出的电压和施加到发射单元的电压电压，其中所述第二接地端子电压高于所述第一接地端子电压，以将低于参考电压的电压施加到所述第二薄膜晶体管。

10. 发明授权

US07245080B2 Substrate having organic electroluminescent device and method of fabricating the same 有权
标题翻译：具有有机电致发光器件的衬底及其制造方法
公开(公告)号：US07245080B2
公开(公告)日：2007-07-17
申请号：US11430137
申请日：2006-05-09
申请人： Jae-Yoon Lee , Kyung-Man Kim , Jae-Yong Park , Choong-Keun Yoo , Ock-Hee Kim
发明人： Jae-Yoon Lee , Kyung-Man Kim , Jae-Yong Park , Choong-Keun Yoo , Ock-Hee Kim
IPC分类号： H01J17/02
CPC分类号： H01L27/3251 , H01L27/3246 , H01L51/56
摘要： An organic electroluminescent device includes first and second substrates facing and spaced apart from each other, the first and second substrates including a pixel region; a gate line on an inner surface of the first substrate; a data line crossing the gate line; a switching thin film transistor connected with the gate line and the data line; a driving thin film transistor connected with the switching thin film transistor; a power line connected with the driving thin film transistor; a first electrode on an inner surface of the second substrate; a first sidewall and a second sidewall on the first electrode at a boundary of the pixel region, the first sidewall and the second sidewall spaced apart from each other; an electroluminescent layer on the first electrode in the pixel region; a second electrode on the electroluminescent layer in the pixel region; and a connection electrode electrically connected to the first and second substrates.
摘要翻译：有机电致发光器件包括面对并彼此间隔开的第一和第二衬底，第一和第二衬底包括像素区域; 在第一基板的内表面上的栅极线; 跨越栅极线的数据线; 与栅极线和数据线连接的开关薄膜晶体管; 与开关薄膜晶体管连接的驱动薄膜晶体管; 与驱动薄膜晶体管连接的电源线; 在所述第二基板的内表面上的第一电极; 第一侧壁和第二侧壁在第一电极上在像素区域的边界处，第一侧壁和第二侧壁彼此间隔开; 像素区域中的第一电极上的电致发光层; 在像素区域中的电致发光层上的第二电极; 以及电连接到第一和第二基板的连接电极。

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