专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070048957A1 METHOD OF MANUFACTURING A CHARGE-TRAPPING DIELECTRIC AND METHOD OF MANUFACTURING A SONOS-TYPE NON-VOLATILE SEMICONDUCTOR DEVICE 有权
标题翻译：电荷捕捉介质的制造方法和制造SONOS型非挥发性半导体器件的方法
公开(公告)号：US20070048957A1
公开(公告)日：2007-03-01
申请号：US11468944
申请日：2006-08-31
申请人： Sung-Hae LEE , Ju-Wan LIM , Jae-Young AHN , Sang-Ryol YANG , Ki-Hyun HWANG
发明人： Sung-Hae LEE , Ju-Wan LIM , Jae-Young AHN , Sang-Ryol YANG , Ki-Hyun HWANG
IPC分类号： H01L21/8228
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4234 , Y10S438/954
摘要： In an embodiment, a method of manufacturing a charge-trapping dielectric and a silicon-oxide-nitride-oxide-silicon (SONOS)-type non-volatile semiconductor device includes forming the charge-trapping dielectric, and a first oxide layer including silicon oxide. A silicon nitride layer including silicon-rich nitride is formed by a cyclic chemical vapor deposition (CVD) process using a silicon source material and a nitrogen source gas. A second oxide layer is formed on the silicon nitride layer. Hence, the charge-trapping dielectric having good erase characteristics is formed. In the SONOS-type non-volatile semiconductor device including the charge-trapping dielectric, a data erase process may be stably performed.
摘要翻译：在一个实施例中，制造电荷俘获电介质和氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体器件的方法包括形成电荷俘获电介质和包含氧化硅的第一氧化物层。通过使用硅源材料和氮源气体的循环化学气相沉积（CVD）工艺形成包括富含硅的氮化物的氮化硅层。在氮化硅层上形成第二氧化物层。因此，形成具有良好擦除特性的电荷俘获电介质。在包含电荷捕获电介质的SONOS型非易失性半导体器件中，可以稳定地执行数据擦除处理。

2. 发明申请

US20120153291A1 Vertical Memory Devices Including Indium And/Or Gallium Channel Doping 有权
标题翻译：包括铟和/或镓通道掺杂的垂直存储器件
公开(公告)号：US20120153291A1
公开(公告)日：2012-06-21
申请号：US13298728
申请日：2011-11-17
申请人： Jin-Gyun KIM , Ki-Hyun HWANG , Sung-Hae LEE , Ji-Hoon CHOI
发明人： Jin-Gyun KIM , Ki-Hyun HWANG , Sung-Hae LEE , Ji-Hoon CHOI
IPC分类号： H01L29/792 , H01L29/04
CPC分类号： H01L29/7926 , H01L27/11582 , H01L29/1041 , H01L29/167 , H01L29/7923
摘要： A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed.
摘要翻译：垂直存储器件可以包括衬底，衬底上的第一选择线，第一选择线上的多个字线，多个字线上的第二选择线，以及半导体沟道。第一选择线可以在多个字线和衬底之间，并且多个字线可以在第一和第二选择线之间。此外，第一选择线和第二选择线和多个字线可以在与衬底的表面垂直的方向上间隔开。半导体通道可以延伸离开衬底的与第一和第二选择线和多个字线的侧壁相邻的表面。此外，与第二选择线相邻的半导体通道的部分可以掺杂铟和/或镓。还讨论了相关方法。

3. 发明申请

US20140054675A1 VERTICAL TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：垂直型半导体器件及其制造方法
公开(公告)号：US20140054675A1
公开(公告)日：2014-02-27
申请号：US13945336
申请日：2013-07-18
申请人： Chae-Ho Kim , Sung-Hae Lee , Toshiro Nakanishi , Dong-Woo Kim
发明人： Sung-Hae LEE , Toshiro NAKANISHI , Dong-Woo KIM , Chae-Ho KIM
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L29/7926 , H01L27/11582 , H01L29/66666 , H01L29/66833
摘要： According to example embodiments, a vertical type semiconductor device includes a pillar structure on a substrate. The pillar structure includes a semiconductor pattern and a channel pattern. The semiconductor pattern includes an impurity region. A first word line structure faces the channel pattern and is horizontally extended while surrounding the pillar structure. A second word line structure has one side facing the impurity region of the semiconductor pattern and another side facing the substrate. A common source line is provided at a substrate portion adjacent to a sidewall end portion of the second word line structure.
摘要翻译：根据示例性实施例，垂直型半导体器件包括在衬底上的柱结构。柱结构包括半导体图案和沟道图案。半导体图案包括杂质区域。第一字线结构面向通道图案，并且在围绕柱结构的同时水平延伸。第二字线结构具有面向半导体图案的杂质区域和面向衬底的另一侧的一侧。在与第二字线结构的侧壁端部相邻的衬底部分处提供公共源极线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式