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1. 发明申请

US20120051162A1 METHOD AND APPARATUS FOR BIT CELL REPAIR 有权
标题翻译：用于位单元修复的方法和装置
公开(公告)号：US20120051162A1
公开(公告)日：2012-03-01
申请号：US12871417
申请日：2010-08-30
申请人： Sung-Chieh Lin , Jiann-Tseng Huang , Wei-Li Liao , Kuoyuan Hsu
发明人： Sung-Chieh Lin , Jiann-Tseng Huang , Wei-Li Liao , Kuoyuan Hsu
IPC分类号： G11C29/04
CPC分类号： G11C29/04 , G11C29/44
摘要： A method includes reading data from a subset of a plurality of memory bit cells of a non-volatile memory. The data identifies an address of at least one individual failed bit cell. The method further includes loading the data directly into a register, receiving an address of data to be accessed, determining if the received address is the address of any individual failed bit cell; and accessing the data of the register if the received address is the address of any individual failed bit cell.
摘要翻译：一种方法包括从非易失性存储器的多个存储位单元的子集读取数据。数据标识至少一个单独故障位单元的地址。该方法还包括将数据直接加载到寄存器中，接收要访问的数据的地址，确定接收的地址是否是任何单个故障位单元的地址; 并且如果接收到的地址是任何单个故障位单元的地址，则访问寄存器的数据。

2. 发明授权

US08467258B2 Method and apparatus for bit cell repair 有权
公开(公告)号：US08467258B2
公开(公告)日：2013-06-18
申请号：US12871417
申请日：2010-08-30
申请人： Sung-Chieh Lin , Jiann-Tseng Huang , Wei-Li Liao , Kuoyuan Hsu
发明人： Sung-Chieh Lin , Jiann-Tseng Huang , Wei-Li Liao , Kuoyuan Hsu
IPC分类号： G11C29/04
CPC分类号： G11C29/04 , G11C29/44
摘要： A method includes reading data from a subset of a plurality of memory bit cells of a non-volatile memory. The data identifies an address of at least one individual failed bit cell. The method further includes loading the data directly into a register, receiving an address of data to be accessed, determining if the received address is the address of any individual failed bit cell; and accessing the data of the register if the received address is the address of any individual failed bit cell.

3. 发明授权

US08427857B2 Electrical fuse programming time control scheme 有权
标题翻译：电熔丝编程时间控制方案
公开(公告)号：US08427857B2
公开(公告)日：2013-04-23
申请号：US12774851
申请日：2010-05-06
申请人： Po-Hung Chen , Sung-Chieh Lin , Kuoyuan Hsu , Jiann-Tseng Huang
发明人： Po-Hung Chen , Sung-Chieh Lin , Kuoyuan Hsu , Jiann-Tseng Huang
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.
摘要翻译：电路包括熔丝和感测和控制电路。熔丝耦合在MOS晶体管和电流源节点之间。感测和控制电路被配置为接收编程脉冲并将修改的编程信号输出到MOS晶体管的栅极，以编程保险丝。改进的编程信号具有基于通过第一保险丝的电流的幅度的脉冲宽度。

4. 发明授权

US08207783B2 Circuit and method for characterizing the performance of a sense amplifier 有权
标题翻译：用于表征读出放大器性能的电路和方法
公开(公告)号：US08207783B2
公开(公告)日：2012-06-26
申请号：US12856824
申请日：2010-08-16
申请人： Wei-Li Liao , Sung-Chieh Lin , Kuoyuan Hsu
发明人： Wei-Li Liao , Sung-Chieh Lin , Kuoyuan Hsu
IPC分类号： H01H37/76
CPC分类号： G11C29/026 , G11C29/028
摘要： An integrated circuit includes a sensing circuit, a fuse box, and a fuse bus decoder. The sensing circuit includes an output node, and the fuse box includes a plurality of switches coupled in series with a plurality of resistive elements. The fuse box is coupled to the output node of the sensing circuit from which the fuse box is configured to receive a current. The fuse bus decoder is coupled to the fuse box and includes at least one demultiplexer configured to receive a signal and in response output a plurality of control signals for selectively opening and closing the switches of the fuse box to adjust a resistance across the fuse box. A voltage of the output node of the sense amplifier is based on a resistance the fuse box and the current.
摘要翻译：集成电路包括感测电路，保险丝盒和熔丝总线解码器。感测电路包括输出节点，并且保险丝盒包括与多个电阻元件串联耦合的多个开关。保险丝盒耦合到感测电路的输出节点，保险丝盒从该感应电路的输出节点配置为接收电流。熔丝总线解码器耦合到保险丝盒，并且包括至少一个多路分解器，其被配置为接收信号，并且响应于输出多个控制信号，用于选择性地打开和闭合保险丝盒的开关以调整保险丝盒两端的电阻。读出放大器的输出节点的电压基于保险丝盒和电流的电阻。

5. 发明授权

US08432759B2 Measuring electrical resistance 有权
标题翻译：测量电阻
公开(公告)号：US08432759B2
公开(公告)日：2013-04-30
申请号：US12824652
申请日：2010-06-28
申请人： Kuoyuan Hsu , Po-Hung Chen , Jiann-Tseng Huang , Subramani Kengeri
发明人： Kuoyuan Hsu , Po-Hung Chen , Jiann-Tseng Huang , Subramani Kengeri
IPC分类号： G11C7/00 , G11C17/18
CPC分类号： G11C13/00 , G11C5/147 , G11C7/00 , G11C7/062 , G11C7/22 , G11C13/0004 , G11C13/004 , G11C16/26 , G11C17/16 , G11C17/165 , G11C17/18 , G11C2013/0045
摘要： A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.
摘要翻译：一种具有第一电路的电路，其被配置为接收输入电压并产生产生流过电阻器件的第一电流的第一电压和产生第二电流的第二电压; 电耦合到所述电阻装置并具有产生第三电流的第三电压的节点; 以及第二电路，被配置为产生具有指示电阻装置的逻辑状态的逻辑状态的第四电压。

6. 发明授权

US09280633B2 Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US09280633B2
公开(公告)日：2016-03-08
申请号：US14279406
申请日：2014-05-16
申请人： Young Seog Kim , Kuoyuan Hsu , Jacklyn Chang
发明人： Young Seog Kim , Kuoyuan Hsu , Jacklyn Chang
IPC分类号： G11C15/00 , G06F17/50 , G11C15/04 , H03K19/20
CPC分类号： G06F17/5072 , G11C15/04 , H03K19/20
摘要： A method of designing a content-addressable memory (CAM) includes associating CAM cells with a summary circuit. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. Logic gates in at least one of the first level of logic gates or the second level of logic gates are selected to have an odd number of input pins so that an input pin and an output pin share a layout sub-slot.
摘要翻译：设计内容寻址存储器（CAM）的方法包括将CAM单元与汇总电路相关联。汇总电路包括第一级逻辑门和第二级逻辑门。第一级逻辑门具有各自被配置为接收多个CAM单元中对应的一个的单元的输出的输入。逻辑门的第二级具有各自被配置为接收第一级逻辑门的对应的一个的输出的输入。选择第一级逻辑门或第二级逻辑门中的至少一个的逻辑门具有奇数个输入引脚，使得输入引脚和输出引脚共享布局子时隙。

7. 发明授权

US06798687B2 System and method for effectively implementing a high speed DRAM device 失效
标题翻译：有效实施高速DRAM器件的系统和方法
公开(公告)号：US06798687B2
公开(公告)日：2004-09-28
申请号：US10320056
申请日：2002-12-16
申请人： Kuoyuan Hsu , Gary Chang , Patrick Chuang
发明人： Kuoyuan Hsu , Gary Chang , Patrick Chuang
IPC分类号： G11C700
CPC分类号： G11C7/1096 , G11C7/1078 , G11C11/4076 , G11C2207/229
摘要： A system and method for effectively implementing a high-speed DRAM device may include memory cells that each have a bitline for transferring storage data, a wordline for enabling an accelerated-write operation in the memory cell, and a data storage node with a corresponding cell voltage. An accelerated-write circuit may then directly provide the storage data to an appropriate bitline in a pre-toggled state in response to one or more accelerated-write enable signals. The corresponding cell voltage may therefore begin a state-change transition towards the pre-toggled state immediately after the wordline is activated to successfully reach a full-state level before the wordline is deactivated during a high-speed memory cycle.
摘要翻译：用于有效实现高速DRAM设备的系统和方法可以包括每个具有用于传送存储数据的位线的存储器单元，用于在存储单元中启用加速写入操作的字线以及具有相应单元的数据存储节点电压。响应于一个或多个加速写入使能信号，加速写入电路然后可以以预切换状态直接将存储数据提供给适当的位线。因此，在高速存储器周期中，在字线被禁用之前，相应的单元电压可能在字线被激活以成功地达到满状态电平之后立即开始朝向预切换状态的状态转变。

8. 发明授权

US08395920B2 Content addressable memory design 有权
标题翻译：内容可寻址内存设计
公开(公告)号：US08395920B2
公开(公告)日：2013-03-12
申请号：US12788924
申请日：2010-05-27
申请人： Young Seog Kim , Kuoyuan Hsu , Jacklyn Chang
发明人： Young Seog Kim , Kuoyuan Hsu , Jacklyn Chang
IPC分类号： G11C15/00
CPC分类号： G06F17/5072 , G11C15/04 , H03K19/20
摘要： A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data is received, memory cells M provide compared data for corresponding comparators C in CAM cells B to compare the compared data to the received data. If all compared data match all received data lines for an entry, then there is a hit for that entry. But if any compared data does not match the corresponding data line, then there is a miss for that line and therefore a miss for that entry. Depending on applications, the CAM returns an address if there is a hit for one or a plurality of entries.
摘要翻译：静态CAM包括多个条目E，每个条目E包括多个CAM单元B和概要S.每个CAM单元B与存储单元M和比较器C相关联。通常，CAM接收到i个查找数据线条。当接收到数据时，存储器单元M提供CAM单元B中对应的比较器C的比较数据，以将比较的数据与接收到的数据进行比较。如果所有比较的数据匹配所有接收到的数据行的条目，则该条目的命中。但是，如果任何比较的数据与相应的数据行不匹配，那么该行有一个缺失，因此该条目的缺失。根据应用程序，如果有一个或多个条目的命中，CAM将返回一个地址。

9. 发明授权

US08378654B2 Voltage regulator with high accuracy and high power supply rejection ratio 有权
标题翻译：电压调节器具有高精度和高电源抑制比
公开(公告)号：US08378654B2
公开(公告)日：2013-02-19
申请号：US12750260
申请日：2010-03-30
申请人： Chan-Hong Chern , Tzu Ching Chang , Min-Shueh Yuan , Yuwen Swei , Chih-Chang Lin , Chiang Pu , Ming-Chieh Huang , Kuoyuan Hsu
发明人： Chan-Hong Chern , Tzu Ching Chang , Min-Shueh Yuan , Yuwen Swei , Chih-Chang Lin , Chiang Pu , Ming-Chieh Huang , Kuoyuan Hsu
IPC分类号： G05F1/44
CPC分类号： H02M3/158 , G05F1/44 , G05F1/56
摘要： A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor's gate. The PMOS transistor's source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp's second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp's first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.
摘要翻译：提供了具有高精度和电源抑制比（PSRR）的稳压电路。在一个实施例中，具有到反相输入的电压参考输入的运算放大器具有连接到PMOS晶体管的栅极的第一输出。 PMOS晶体管的源极和漏极各自连接到电源和稳压器输出。电压调节器输出连接到偏置在饱和模式的NMOS晶体管和一系列两个电阻。运算放大器的非反相输入端连接在第一个反馈回路的两个电阻之间。运算放大器的第二个输出通过用于第二反馈回路的交流耦合电容器连接到NMOS晶体管的栅极。运算放大器的第一个输出可以通过电容连接到电源电压，以进一步提高高频PSRR。在另一个实施例中，PMOS和NMOS晶体管的作用相反。

10. 发明授权

US08164974B2 Memory circuits, systems, and method of interleaving accesses thereof 有权
标题翻译：存储器电路，系统及其访问方法
公开(公告)号：US08164974B2
公开(公告)日：2012-04-24
申请号：US12698423
申请日：2010-02-02
申请人： Kuoyuan Hsu , Ming-Chieh Huang , Young Suk Kim , Subramani Kengeri
发明人： Kuoyuan Hsu , Ming-Chieh Huang , Young Suk Kim , Subramani Kengeri
IPC分类号： G11C11/00
CPC分类号： G11C7/1042 , G11C8/04
摘要： An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.
摘要翻译：交错存储器电路包括具有第一存储单元的第一存储器组。第一本地控制电路与第一存储体耦合。第二存储器组包括第二存储器单元。第二本地控制电路与第二存储体耦合。 IO块与第一存储体和第二存储体耦合。全局控制电路与第一和第二本地控制电路耦合。交织接入包括具有第一周期和第二周期的时钟信号，用于分别访问第一存储器单元和第二存储单元，其中第二周期能够使第一本地控制电路触发第一读取列选择信号RSSL用于访问第一个存储单元。

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