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1. 发明授权

US08537632B2 Method of erasing semiconductor memory device 有权
标题翻译：擦除半导体存储器件的方法
公开(公告)号：US08537632B2
公开(公告)日：2013-09-17
申请号：US13095156
申请日：2011-04-27
申请人： Hea Jong Yang , Hee Youl Lee , Sung Jae Chung , Hyun Heo , Jeong Hyong Yi , Yong Dae Park
发明人： Hea Jong Yang , Hee Youl Lee , Sung Jae Chung , Hyun Heo , Jeong Hyong Yi , Yong Dae Park
IPC分类号： G11C7/00
CPC分类号： G11C16/0483 , G11C16/16 , G11C16/32
摘要： A method of erasing a semiconductor memory device comprises grouping a plurality of word lines of each memory block into at least two groups based on intensity of disturbance between neighboring word lines; performing an erase operation by applying a ground voltage to all word lines of a selected memory block and by applying an erase voltage to a well of the selected memory block; and first increasing the ground voltage of one group of the groups to a positive voltage during the erase operation.
摘要翻译：擦除半导体存储器件的方法包括：基于相邻字线之间的干扰强度将每个存储器块的多个字线分组成至少两组; 通过对所选择的存储块的所有字线施加接地电压并通过向所选存储块的阱施加擦除电压来执行擦除操作; 并且在擦除操作期间首先将一组组的接地电压增加到正电压。

2. 发明授权

US07957191B2 Method of programming non-volatile memory device 有权
标题翻译：非易失性存储器件编程方法
公开(公告)号：US07957191B2
公开(公告)日：2011-06-07
申请号：US12132068
申请日：2008-06-03
申请人： Sung Jae Chung
发明人： Sung Jae Chung
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： A method of programming a non-volatile memory device includes applying a power supply voltage to a drain select line, applying a high level voltage to a drain-side pass word line or a source-side pass word line, and applying a pass voltage to unselected word lines and a program voltage to a selected word line. The high level voltage is applied to the drain-side pass word line or the source-side pass word line before applying the pass voltage to the unselected word lines and the program voltage to the selected word line.
摘要翻译：一种对非易失性存储器件进行编程的方法包括将电源电压施加到漏极选择线，向漏极侧通过字线或源极通过字线施加高电平电压，并将通过电压施加到未选字线和编程电压到所选字线。在将通过电压施加到未选择的字线和对所选择的字线的编程电压之前，将高电平电压施加到漏极侧通过字线或源极通过字线。

3. 发明授权

US08634251B2 Program method of semiconductor memory device 有权
标题翻译：半导体存储器件的编程方法
公开(公告)号：US08634251B2
公开(公告)日：2014-01-21
申请号：US13096733
申请日：2011-04-28
申请人： Sung Jae Chung
发明人： Sung Jae Chung
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C7/12 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C2216/14
摘要： A program method of a semiconductor memory device may include precharging first bit lines, coupled to first strings, to increase a potential level of the first strings to a first potential level; programming memory cells of a selected word line, wherein the memory cells are coupled to second bit lines; pre-discharging the first bit lines to decrease a potential level of the word lines to a second potential level, wherein the second potential level is lower than the first potential level; and discharging the first bit lines and the word lines to a ground voltage after the pre-discharging.
摘要翻译：半导体存储器件的编程方法可以包括对第一串进行预充电的第一位线，以将第一串的电位电平增加到第一电位电平; 编程所选字线的存储单元，其中所述存储单元耦合到第二位线; 对第一位线进行预放电以将字线的电位电平降低到第二电位电平，其中第二电位电平低于第一电位电平; 并且在预放电之后将第一位线和字线放电到接地电压。

4. 发明授权

US07142460B2 Flash memory device with improved pre-program function and method for controlling pre-program operation therein 有权
标题翻译：具有改进的预编程功能的闪存器件和用于控制其中的程序前操作的方法
公开(公告)号：US07142460B2
公开(公告)日：2006-11-28
申请号：US11158463
申请日：2005-06-21
申请人： Hee Youl Lee , Sung Jae Chung
发明人： Hee Youl Lee , Sung Jae Chung
IPC分类号： G11C11/24
CPC分类号： G11C16/16 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/30
摘要： A flash memory device has an improved pre-program function. The flash memory device comprises memory cell blocks each including wordlines, bitlines, and memory cells sharing common source lines; an erase controller generating a pre-program control signal in response to an erase command; and a voltage selection circuit selecting one of first and second common source voltages in response to one among the pre-program control signal, a read command, and a program command and outputting the selected voltage to a global common source line.
摘要翻译：闪存设备具有改进的预编程功能。闪存器件包括存储单元块，每个存储单元块包括字线，位线和共享公共源极线的存储器单元; 擦除控制器，其响应于擦除命令产生预编程控制信号; 以及电压选择电路，响应于所述预编程控制信号，读命令和编程命令中的一个选择第一和第二公共源电压中的一个，并将所选择的电压输出到全局公共源线。

5. 发明申请

US20110261623A1 METHOD OF ERASING SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：擦除半导体存储器件的方法
公开(公告)号：US20110261623A1
公开(公告)日：2011-10-27
申请号：US13095156
申请日：2011-04-27
申请人： Hea Jong YANG , Hee Youl Lee , Sung Jae Chung , Hyun Heo , Jeong Hyong Yi , Yong Dae Park
发明人： Hea Jong YANG , Hee Youl Lee , Sung Jae Chung , Hyun Heo , Jeong Hyong Yi , Yong Dae Park
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/16 , G11C16/32
摘要： A method of erasing a semiconductor memory device comprises grouping a plurality of word lines of each memory block into at least two groups based on intensity of disturbance between neighboring word lines; performing an erase operation by applying a ground voltage to all word lines of a selected memory block and by applying an erase voltage to a well of the selected memory block; and first increasing the ground voltage of one group of the groups to a positive voltage during the erase operation.
摘要翻译：擦除半导体存储器件的方法包括：基于相邻字线之间的干扰强度将每个存储器块的多个字线分组成至少两组; 通过对所选择的存储块的所有字线施加接地电压并通过向所选存储块的阱施加擦除电压来执行擦除操作; 并且在擦除操作期间首先将一组组的接地电压增加到正电压。

6. 发明授权

US06960805B2 Flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell 有权
标题翻译：闪存单元及其制造方法，以及闪存单元中的编程/擦除/读取方法
公开(公告)号：US06960805B2
公开(公告)日：2005-11-01
申请号：US10750850
申请日：2004-01-05
申请人： Byung Jin Ahn , Byung Soo Park , Sung Jae Chung
发明人： Byung Jin Ahn , Byung Soo Park , Sung Jae Chung
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0475 , H01L21/84 , H01L27/115 , H01L27/1203
摘要： The present invention relates to a flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell. According to the present invention, a source region and a drain region are first formed and a tunnel oxide film is then formed. Therefore, it is possible to prevent damage of the tunnel oxide film due to an ion implantation process. Further, independent two channel regions are formed below the floating gate. Thus, it is possible to store data of two or more bits at a single cell. In addition, the tunnel oxide film, the floating gate and the dielectric film having an ONO structure are formed at a given regions. It is thus possible to reduce the steps of a process and improve an electrical characteristic and integration level of a device.
摘要翻译：本发明涉及一种闪存单元及其制造方法，以及闪存单元中的编程/擦除/读取方法。根据本发明，首先形成源极区域和漏极区域，然后形成隧道氧化膜。因此，可以防止由于离子注入工艺而引起的隧道氧化膜的损坏。此外，在浮动栅极下方形成独立的两个沟道区域。因此，可以在单个单元存储两个或多个位的数据。此外，隧道氧化物膜，浮栅和具有ONO结构的电介质膜形成在给定的区域。因此，可以减少处理的步骤并提高装置的电气特性和集成度。

7. 发明授权

US06703275B2 Flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell 有权
标题翻译：闪存单元及其制造方法，以及闪存单元中的编程/擦除/读取方法
公开(公告)号：US06703275B2
公开(公告)日：2004-03-09
申请号：US10287781
申请日：2002-11-05
申请人： Byung Jin Ahn , Byung Soo Park , Sung Jae Chung
发明人： Byung Jin Ahn , Byung Soo Park , Sung Jae Chung
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , G11C16/0475 , H01L21/84 , H01L27/115 , H01L27/1203
摘要： The present invention relates to a flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell. According to the present invention, a source region and a drain region are first formed and a tunnel oxide film is then formed. Therefore, it is possible to prevent damage of the tunnel oxide film due to an ion implantation process. Further, independent two channel regions are formed below the floating gate. Thus, it is possible to store data of two or more bits at a single cell. In addition, the tunnel oxide film, the floating gate and the dielectric film having an ONO structure are formed at a given regions. It is thus possible to reduce the steps of a process and improve an electrical characteristic and integration level of a device.
摘要翻译：本发明涉及一种闪存单元及其制造方法，以及闪存单元中的编程/擦除/读取方法。根据本发明，首先形成源极区域和漏极区域，然后形成隧道氧化膜。因此，可以防止由于离子注入工艺而引起的隧道氧化膜的损坏。此外，在浮动栅极下方形成独立的两个沟道区域。因此，可以在单个单元存储两个或多个位的数据。此外，隧道氧化物膜，浮栅和具有ONO结构的电介质膜形成在给定的区域。因此，可以减少处理的步骤并提高装置的电气特性和集成度。

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