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1. 发明授权

US07998851B2 Semiconductor devices having contact plugs with stress buffer spacers and methods of fabricating the same 有权
标题翻译：具有接触插塞和应力缓冲垫片的半导体器件及其制造方法
公开(公告)号：US07998851B2
公开(公告)日：2011-08-16
申请号：US12715599
申请日：2010-03-02
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
IPC分类号： H01L21/36
CPC分类号： H01L29/7842 , H01L21/823425 , H01L21/823475 , H01L27/0688
摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

2. 发明授权

US08481416B2 Semiconductor devices having contact plugs with stress buffer spacers and methods of fabricating the same 有权
标题翻译：具有接触插塞和应力缓冲垫片的半导体器件及其制造方法
公开(公告)号：US08481416B2
公开(公告)日：2013-07-09
申请号：US13205461
申请日：2011-08-08
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
IPC分类号： H01L21/20
CPC分类号： H01L29/7842 , H01L21/823425 , H01L21/823475 , H01L27/0688
摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

3. 发明申请

US20110300704A1 SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS WITH STRESS BUFFER SPACERS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有应力缓冲垫片的接触片的半导体器件及其制造方法
公开(公告)号：US20110300704A1
公开(公告)日：2011-12-08
申请号：US13205461
申请日：2011-08-08
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
IPC分类号： H01L21/283
CPC分类号： H01L29/7842 , H01L21/823425 , H01L21/823475 , H01L27/0688
摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

4. 发明申请

US20100159689A1 SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS WITH STRESS BUFFER SPACERS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有应力缓冲垫片的接触片的半导体器件及其制造方法
公开(公告)号：US20100159689A1
公开(公告)日：2010-06-24
申请号：US12715599
申请日：2010-03-02
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
IPC分类号： H01L21/768
CPC分类号： H01L29/7842 , H01L21/823425 , H01L21/823475 , H01L27/0688
摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

5. 发明授权

US07393700B2 Low temperature methods of etching semiconductor substrates 有权
标题翻译：低温半导体衬底蚀刻方法
公开(公告)号：US07393700B2
公开(公告)日：2008-07-01
申请号：US11208490
申请日：2005-08-22
申请人： Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , Deok-Hyung Lee , In-Soo Jung , Young-Eun Lee
发明人： Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , Deok-Hyung Lee , In-Soo Jung , Young-Eun Lee
IPC分类号： H01L21/302
CPC分类号： H01L29/66636 , H01L21/3065 , H01L21/32135 , H01L29/165 , H01L29/66628
摘要： Methods of etching a semiconductor substrate may include providing a first gas that is chemically reactive with respect to the semiconductor substrate, and while providing the first gas, providing a second gas different than the first gas. More particularly, a molecule of the second gas may include a hydrogen atom, and the second gas may lower a temperature at which the first gas chemically reacts with the semiconductor substrate. The mixture of the first and second gases may be provided adjacent the semiconductor substrate to etch the semiconductor substrate.
摘要翻译：蚀刻半导体衬底的方法可以包括提供相对于半导体衬底具有化学反应性的第一气体，并且在提供第一气体的同时，提供不同于第一气体的第二气体。更具体地，第二气体的分子可以包括氢原子，第二气体可以降低第一气体与半导体衬底发生化学反应的温度。第一和第二气体的混合物可以设置在邻近半导体衬底处以蚀刻半导体衬底。

6. 发明申请

US20060057821A1 Low temperature methods of etching semiconductor substrates 有权
标题翻译：低温半导体衬底蚀刻方法
公开(公告)号：US20060057821A1
公开(公告)日：2006-03-16
申请号：US11208490
申请日：2005-08-22
申请人： Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , Deok-Hyung Lee , In-Soo Jung , Young-Eun Lee
发明人： Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , Deok-Hyung Lee , In-Soo Jung , Young-Eun Lee
IPC分类号： H01L21/30
CPC分类号： H01L29/66636 , H01L21/3065 , H01L21/32135 , H01L29/165 , H01L29/66628
摘要： Methods of etching a semiconductor substrate may include providing a first gas that is chemically reactive with respect to the semiconductor substrate, and while providing the first gas, providing a second gas different than the first gas. More particularly, a molecule of the second gas may include a hydrogen atom, and the second gas may lower a temperature at which the first gas chemically reacts with the semiconductor substrate. The mixture of the first and second gases may be provided adjacent the semiconductor substrate to etch the semiconductor substrate.
摘要翻译：蚀刻半导体衬底的方法可以包括提供相对于半导体衬底具有化学反应性的第一气体，并且在提供第一气体的同时，提供不同于第一气体的第二气体。更具体地，第二气体的分子可以包括氢原子，第二气体可以降低第一气体与半导体衬底发生化学反应的温度。第一和第二气体的混合物可以设置在邻近半导体衬底处以蚀刻半导体衬底。

7. 发明申请

US20050248035A1 Semiconductor devices having contact plugs with stress buffer spacers and methods of fabricating the same 审中-公开
标题翻译：具有接触插塞和应力缓冲垫片的半导体器件及其制造方法
公开(公告)号：US20050248035A1
公开(公告)日：2005-11-10
申请号：US11092524
申请日：2005-03-29
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee , Sun-Ghil Lee , In-Soo Jung , Young-Eun Lee , Deok-Hyung Lee
IPC分类号： H01L21/28 , H01L21/8234 , H01L23/48 , H01L23/52 , H01L27/06 , H01L29/40
CPC分类号： H01L29/7842 , H01L21/823425 , H01L21/823475 , H01L27/0688
摘要： A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底上的无机绝缘层，延伸穿过无机绝缘层以接触半导体衬底的接触插塞和设置在节点接触插塞和无机绝缘层之间的应力缓冲间隔件。该器件还包括设置在无机绝缘层上并具有沿着无机绝缘层延伸以接触接触插塞的源极/漏极区域的薄膜晶体管（TFT）。该器件还可以包括插入无机绝缘层和半导体衬底之间的蚀刻停止层。

8. 发明申请

US20060079056A1 Semiconductor structures having a strained silicon layer on a silicon-germanium layer and related fabrication methods 审中-公开
标题翻译：在硅锗层上具有应变硅层的半导体结构和相关的制造方法
公开(公告)号：US20060079056A1
公开(公告)日：2006-04-13
申请号：US11247412
申请日：2005-10-11
申请人： Young-Pil Kim , Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , In-Soo Jung
发明人： Young-Pil Kim , Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , In-Soo Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/02579 , H01L21/02639 , H01L29/78
摘要： A semiconductor structure including a SiGe layer and a method of fabricating the same are provided. The structure includes a silicon layer heavily doped with impurities. A SiGe layer is disposed on the silicon layer. A strained silicon layer is disposed on the SiGe layer. The impurities may be boron. The boron in the silicon layer may have a concentration of 1016 to 1020/cm3. Boron in the SiGe layer, diffused from the silicon substrate or directly doped, may suppress movement of misfit dislocation occurring in the SiGe layer toward the surface, thereby reducing a threading dislocation density near the surface of the strained silicon layer.
摘要翻译：提供了包括SiGe层的半导体结构及其制造方法。该结构包括重掺杂杂质的硅层。 SiGe层设置在硅层上。应变硅层设置在SiGe层上。杂质可以是硼。硅层中的硼可以具有10 16至10 20 / cm 3的浓度。在SiGe层中从硅衬底扩散或直接掺杂的硼可以抑制SiGe层中发生的失配位错的移动朝向表面，由此降低应变硅层表面附近的穿透位错密度。

9. 发明申请

US20090130826A1 Method of Forming a Semiconductor Device Having a Strained Silicon Layer on a Silicon-Germanium Layer 审中-公开
标题翻译：在硅锗层上形成具有应变硅层的半导体器件的方法
公开(公告)号：US20090130826A1
公开(公告)日：2009-05-21
申请号：US12330796
申请日：2008-12-09
申请人： Young-Pil Kim , Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , In-Soo Jung
发明人： Young-Pil Kim , Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , In-Soo Jung
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L29/1054 , H01L29/66651 , H01L29/78
摘要： A method of forming a semiconductor device having a strained silicon (Si) layer on a silicon germanium (SiGe) layer is provided. The method includes preparing a silicon substrate. A SiGe layer is formed on the silicon substrate. At least a part of the SiGe layer has a first dislocation density. A strained Si layer having a second dislocation density lower than the first dislocation density is formed on the SiGe layer.
摘要翻译：提供了在硅锗（SiGe）层上形成具有应变硅（Si）层的半导体器件的方法。该方法包括制备硅衬底。在硅衬底上形成SiGe层。至少一部分SiGe层具有第一位错密度。在SiGe层上形成具有低于第一位错密度的第二位错密度的应变Si层。

10. 发明申请

US20090239348A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090239348A1
公开(公告)日：2009-09-24
申请号：US12478345
申请日：2009-06-04
申请人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
发明人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
IPC分类号： H01L21/336
CPC分类号： C30B29/06 , C30B15/00
摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
摘要翻译：公开了一种形成在应变硅层上的半导体器件及其制造方法。根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

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