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1. 发明授权

US5909393A Method and apparatus for reading analog values stored in floating gate NAND structures 失效
标题翻译：用于读取存储在浮动栅极NAND结构中的模拟值的方法和装置
公开(公告)号：US5909393A
公开(公告)日：1999-06-01
申请号：US887108
申请日：1997-07-01
申请人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
发明人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C27/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C16/32 , G11C7/16
摘要： This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.
摘要翻译：本发明在模拟存储和重放设备中利用NAND存储单元结构的小单元大小。这部分地通过使用特殊的零电流存储单元实现，其中在读取模式下，电池负载电流被波形化以获得最佳动态范围并且避免其他晶体管的串联寄生电阻的电阻效应源节点或漏极节点，并且避免读取路径中所有晶体管的晶体管电导变化。负载电流是波形的，以减少可能的过冲和稳定效应，以在最佳感测时间内实现精细的输出电压分辨率。公开了该方法和替代实施例的细节。

2. 发明授权

US5808938A Method and apparatus for reading analog values stored in floating gate nand structures 失效
标题翻译：用于读取存储在浮动栅极结构中的模拟值的方法和装置
公开(公告)号：US5808938A
公开(公告)日：1998-09-15
申请号：US887307
申请日：1997-07-02
申请人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
发明人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C27/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C16/32 , G11C7/16
摘要： This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.
摘要翻译：本发明在模拟存储和重放设备中利用NAND存储单元结构的小单元大小。这部分地通过使用特殊的零电流存储单元实现，其中在读取模式下，电池负载电流被波形化以获得最佳动态范围并且避免其他晶体管的串联寄生电阻的电阻效应源节点或漏极节点，并且避免读取路径中所有晶体管的晶体管电导变化。负载电流是波形的，以减少可能的过冲和稳定效应，以在最佳感测时间内实现精细的输出电压分辨率。公开了该方法和替代实施例的细节。

3. 发明授权

US5789786A High-Voltage CMOS transistors on a standard CMOS wafer 失效
标题翻译：标准CMOS晶圆上的高电压CMOS晶体管
公开(公告)号：US5789786A
公开(公告)日：1998-08-04
申请号：US756004
申请日：1996-11-25
申请人： Husam Gaffur , Sukyoon Yoon
发明人： Husam Gaffur , Sukyoon Yoon
IPC分类号： H01L21/336 , H01L27/088 , H01L27/092 , H01L29/10 , H01L29/78 , H01L29/72
CPC分类号： H01L29/7835 , H01L27/088 , H01L27/0922 , H01L29/1087 , H01L29/66659 , H01L29/7801
摘要： A low-voltage 0.8-micron CMOS process is modified by implanting arsenic or phosphorus during epitaxy in a p-type substrate starting material to increase the depth of selected n-well areas for the purpose of producing high-voltage transistors on the same substrate in the same CMOS process. Implanting boron in a p-field extension area in a manner which minimizes the dopant in the adjacent field oxide achieves a similar result. That is, breakdown and punch-through voltages are increased. Together, these make CMOS transistors which operate at a higher voltage range than either innovation alone.
摘要翻译：通过在p型衬底起始材料中的外延期间注入砷或磷来修改低电压0.8微米CMOS工艺，以增加所选择的n阱区的深度，以便在同一衬底上产生高压晶体管相同的CMOS工艺。以最小化相邻场氧化物中的掺杂剂的方式将硼掺杂在p场扩展区域中实现了类似的结果。也就是说，故障和穿通电压增加。在一起，这些使CMOS晶体管工作在比任何一个创新更高的电压范围。

4. 发明授权

US5726934A Method and apparatus for analog reading values stored in floating gate structures 失效
标题翻译：存储在浮动门结构中的模拟读取值的方法和装置
公开(公告)号：US5726934A
公开(公告)日：1998-03-10
申请号：US629729
申请日：1996-04-09
申请人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
发明人： Hieu Van Tran , James Brennan, Jr. , Trevor Blyth , Sukyoon Yoon
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C27/00 , G11C29/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C16/32 , G11C7/16
摘要： This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.
摘要翻译：本发明在模拟存储和重放设备中利用NAND存储单元结构的小单元大小。这部分地通过使用特殊的零电流存储单元实现，其中在读取模式下，单元负载电流被波形化以获得最佳动态范围并且避免其他晶体管的串联寄生电阻的电阻效应源节点或漏极节点，并且避免读取路径中所有晶体管的晶体管电导变化。负载电流是波形的，以减少可能的过冲和稳定效应，以在最佳感测时间内实现精细的输出电压分辨率。公开了该方法和替代实施例的细节。

5. 发明授权

US5578855A High-voltage CMOS transistors on a standard CMOS wafer 失效
标题翻译：标准CMOS晶圆上的高电压CMOS晶体管
公开(公告)号：US5578855A
公开(公告)日：1996-11-26
申请号：US429182
申请日：1995-04-26
申请人： Husam Gaffur , Sukyoon Yoon
发明人： Husam Gaffur , Sukyoon Yoon
IPC分类号： H01L21/336 , H01L27/088 , H01L27/092 , H01L29/10 , H01L29/78 , H01L29/76 , H01L21/265
CPC分类号： H01L29/7835 , H01L27/088 , H01L27/0922 , H01L29/1087 , H01L29/66659 , H01L29/7801
摘要： A low-voltage 0.8-micron CMOS process is modified by implanting arsenic or phosphorus during epitaxy in a p-type substrate starting material to increase the depth of selected n-well areas for the purpose of producing high-voltage transistors on the same substrate in the same CMOS process. Implanting boron in a p-field extension area in a manner which minimizes the dopant in the adjacent field oxide achieves a similar result. That is, breakdown and punch-through voltages are increased. Together, these make CMOS transistors which operate at a higher voltage range than either innovation alone.
摘要翻译：通过在p型衬底起始材料中的外延期间注入砷或磷来改进低电压0.8微米CMOS工艺，以增加所选择的n阱区的深度，以在同一衬底上产生高压晶体管相同的CMOS工艺。以最小化相邻场氧化物中的掺杂剂的方式将硼掺杂在p场扩展区域中实现了类似的结果。也就是说，故障和穿通电压增加。在一起，这些使CMOS晶体管工作在比任何一个创新更高的电压范围。

6. 发明授权

US06940122B2 Flash EEPROM unit cell and memory array architecture including the same 失效
标题翻译：闪存EEPROM单元和存储器阵列架构包括相同
公开(公告)号：US06940122B2
公开(公告)日：2005-09-06
申请号：US10689722
申请日：2003-10-22
申请人： Sukyoon Yoon
发明人： Sukyoon Yoon
IPC分类号： H01L27/115 , G11C16/00 , H01L21/8247 , H01L27/148 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： A high-density flash EEPROM (Electrically Erasable Programmable Read Only Memory) unit cell and a memory array architecture including the same are disclosed. The flash EEPROM unit cell comprises a substrate on which field oxide layers are formed for isolating unit cells, a floating gate dielectric layer formed between the adjacent field oxide layers, wherein the floating gate dielectric layer includes a first dielectric layer and a second dielectric layer which are connected in parallel between a source and a drain formed on the substrate, and the thickness of the first dielectric layer is thicker than the second dielectric layer, a floating gate formed on the floating gate dielectric layer, a control gate dielectric layer formed on the floating gate; and a control gate formed on the control gate dielectric layer.
摘要翻译：公开了一种高密度闪存EEPROM（电可擦除可编程只读存储器）单元和包括其的存储器阵列结构。闪速EEPROM单元包括其上形成有用于隔离单元电池的场氧化物层的衬底，形成在相邻的场氧化物层之间的浮置栅介质层，其中该浮栅绝缘层包括第一电介质层和第二电介质层，在形成在基板上的源极和漏极之间并联连接，并且第一电介质层的厚度比第二电介质层厚，形成在浮栅电介质层上的浮置栅极，形成在栅极电介质层上的控制栅极电介质层浮门以及形成在控制栅极介电层上的控制栅极。

7. 发明授权

US06864530B2 High density flash memory architecture with columnar substrate coding 失效
标题翻译：具有柱状衬底编码的高密度闪存架构
公开(公告)号：US06864530B2
公开(公告)日：2005-03-08
申请号：US10360598
申请日：2003-02-06
申请人： Sukyoon Yoon
发明人： Sukyoon Yoon
IPC分类号： G11C16/02 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C10/04
CPC分类号： H01L29/66825
摘要： A flash memory device includes a substrate having first and second wells. The first well is defined within the second well. A plurality of trenches defines the substrate into a plurality of sub-columnar active regions. The trenches is formed within the first well and extends into the second well. A plurality of flash memory cells are formed on each of the sub-columnar active regions.
摘要翻译：闪存器件包括具有第一和第二阱的衬底。第一口井在第二口井内定义。多个沟槽将衬底限定为多个子柱状有源区域。沟槽形成在第一井内并且延伸到第二井中。在每个子柱状活性区域上形成多个闪存单元。

8. 发明授权

US06396737B2 High density flash memory architecture with columnar substrate coding 有权
标题翻译：具有柱状衬底编码的高密度闪存架构
公开(公告)号：US06396737B2
公开(公告)日：2002-05-28
申请号：US09733427
申请日：2000-12-08
申请人： Sukyoon Yoon , Pavel Klinger , Joo Young Yoon
发明人： Sukyoon Yoon , Pavel Klinger , Joo Young Yoon
IPC分类号： G11C1140
CPC分类号： H01L27/11521 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C2211/565 , H01L27/115
摘要： Instead of using a common substrate (101) for each sector of a flash memory, trenches are used to isolate columnar active substrate regions (304) of the substrate (101), and independent access to each of these columnar regions (304) is provided. First, the independent access to each of these columnar regions (304) provides a capability for achieving more precise control over the voltage on the floating gates (106). For example, flash memory in accordance with the present invention is better suited for multi-level storage (storing of more than 1 bit of information per cell). Second, the independent access to each of these columnar regions (304) also provides a capability for areas of flash memory smaller than an entire sector to be erased at one time. Finally, since both programming and erasing is achieved by way of cold electron tunneling from the columnar active substrate region (304), no high voltages need to be applied to either the drain (102) or source (104). This is advantageous in that the minimum distance required by cell punchthrough is reduced. Hence, higher densities of flash memory may be achieved.
摘要翻译：代替对快闪存储器的每个扇区使用公共衬底（101），使用沟槽来隔离衬底（101）的柱状有源衬底区域（304），并且提供对这些柱状区域（304）中的每一个的独立访问。首先，对这些柱状区域（304）中的每一个的独立访问提供了实现对浮动栅极（106）上的电压的更精确控制的能力。例如，根据本发明的闪速存储器更适合于多级存储（每个单元存储超过1位的信息）。第二，对这些柱状区域（304）中的每一个的独立访问还提供了一次能够擦除小于整个扇区的闪存区域的能力。最后，由于通过来自柱状有源衬底区域（304）的冷电子隧穿来实现编程和擦除，所以不需要将高电压施加到漏极（102）或源极（104）。这是有利的，因为电池穿透所需的最小距离减小了。因此，可以实现更高密度的闪速存储器。

9. 发明授权

US06198658B1 High density flash memory architecture with columnar substrate coding 有权
标题翻译：具有柱状衬底编码的高密度闪存架构
公开(公告)号：US06198658B1
公开(公告)日：2001-03-06
申请号：US09415770
申请日：1999-10-08
申请人： Sukyoon Yoon , Pavel Klinger , Joo Young Yoon
发明人： Sukyoon Yoon , Pavel Klinger , Joo Young Yoon
IPC分类号： G11C1140
CPC分类号： H01L27/11521 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C2211/565 , H01L27/115
摘要： Instead of using a common substrate (101) for each sector of a flash memory, trenches are used to isolate columnar active substrate regions (304) of the substrate (101), and independent access to each of these columnar regions (304) is provided. First, the independent access to each of these columnar regions (304) provides a capability for achieving more precise control over the voltage on the floating gates (106). For example, flash memory in accordance with the present invention is better suited for multi-level storage (storing of more than 1 bit of information per cell). Second, the independent access to each of these columnar regions (304) also provides a capability for areas of flash memory smaller than an entire sector to be erased at one time. Finally, since both programming and erasing is achieved by way of cold electron tunneling from the columnar active substrate region (304), no high voltages need to be applied to either the drain (102) or source (104). This is advantageous in that the minimum distance required by cell punchthrough is reduced. Hence, higher densities of flash memory may be achieved.
摘要翻译：代替对快闪存储器的每个扇区使用公共衬底（101），使用沟槽来隔离衬底（101）的柱状有源衬底区域（304），并且提供对这些柱状区域（304）中的每一个的独立访问。首先，对这些柱状区域（304）中的每一个的独立访问提供了实现对浮动栅极（106）上的电压的更精确控制的能力。例如，根据本发明的闪速存储器更适合于多级存储（每个单元存储超过1位的信息）。第二，对这些柱状区域（304）中的每一个的独立访问还提供了一次能够擦除小于整个扇区的闪存区域的能力。最后，由于通过来自柱状有源衬底区域（304）的冷电子隧穿来实现编程和擦除，所以不需要将高电压施加到漏极（102）或源极（104）。这是有利的，因为电池穿透所需的最小距离减小了。因此，可以实现更高密度的闪速存储器。

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