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1. 发明授权

US08575753B2 Semiconductor device having a conductive structure including oxide and non oxide portions 有权
标题翻译：具有包括氧化物和非氧化物部分的导电结构的半导体器件
公开(公告)号：US08575753B2
公开(公告)日：2013-11-05
申请号：US12787056
申请日：2010-05-25
申请人： Suk-hun Choi , Ki-ho Bae , Yi-koan Hong , Kyung-hyun Kim , Tae-hyun Kim , Kyung-tae Nam , Jun-ho Jeong
发明人： Suk-hun Choi , Ki-ho Bae , Yi-koan Hong , Kyung-hyun Kim , Tae-hyun Kim , Kyung-tae Nam , Jun-ho Jeong
IPC分类号： H01L29/40
CPC分类号： H01L27/228 , H01L21/76831 , H01L21/76834 , H01L21/76856 , H01L21/76888 , H01L23/5228 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1683 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an interlayer insulating layer disposed on a substrate, the interlayer insulating layer comprising an opening exposing the substrate, a barrier layer pattern disposed within the opening, and a conductive pattern disposed on the barrier layer pattern, the conductive pattern having an oxidized portion extending out of the opening and a non-oxidized portion within the opening, wherein a width of the conductive pattern is determined by a thickness of the barrier layer pattern.
摘要翻译：半导体器件包括设置在衬底上的层间绝缘层，所述层间绝缘层包括露出衬底的开口，设置在所述开口内的阻挡层图案以及设置在所述阻挡层图案上的导电图案，所述导电图案具有氧化从开口延伸的部分和开口内的非氧化部分，其中导电图案的宽度由阻挡层图案的厚度确定。

2. 发明申请

US20100301480A1 SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE STRUCTURE 有权
标题翻译：具有导电结构的半导体器件
公开(公告)号：US20100301480A1
公开(公告)日：2010-12-02
申请号：US12787056
申请日：2010-05-25
申请人： SUK-HUN CHOI , Ki-ho Bae , Yi-koan Hong , Kyung-hyun Kim , Tae-hyun Kim , Kyung-tae Nam , Jun-ho Jeong
发明人： SUK-HUN CHOI , Ki-ho Bae , Yi-koan Hong , Kyung-hyun Kim , Tae-hyun Kim , Kyung-tae Nam , Jun-ho Jeong
IPC分类号： H01L23/532 , H01L23/522
CPC分类号： H01L27/228 , H01L21/76831 , H01L21/76834 , H01L21/76856 , H01L21/76888 , H01L23/5228 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1683 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an interlayer insulating layer disposed on a substrate, the interlayer insulating layer comprising an opening exposing the substrate, a barrier layer pattern disposed within the opening, and a conductive pattern disposed on the barrier layer pattern, the conductive pattern having an oxidized portion extending out of the opening and a non-oxidized portion within the opening, wherein a width of the conductive pattern is determined by a thickness of the barrier layer pattern.
摘要翻译：半导体器件包括设置在衬底上的层间绝缘层，所述层间绝缘层包括露出衬底的开口，设置在所述开口内的阻挡层图案以及设置在所述阻挡层图案上的导电图案，所述导电图案具有氧化从开口延伸的部分和开口内的非氧化部分，其中导电图案的宽度由阻挡层图案的厚度确定。

3. 发明授权

US08912592B2 Non-volatile memory device including etch stop layer pattern 有权
标题翻译：包括蚀刻停止层图案的非易失性存储器件
公开(公告)号：US08912592B2
公开(公告)日：2014-12-16
申请号：US13668854
申请日：2012-11-05
申请人： Jong-heun Lim , Ki-ho Bae , Hyo-jung Kim , Kyung-hyun Kim , Chan-wook Seo , Young-beom Pyon
发明人： Jong-heun Lim , Ki-ho Bae , Hyo-jung Kim , Kyung-hyun Kim , Chan-wook Seo , Young-beom Pyon
IPC分类号： H01L29/792 , H01L27/115
CPC分类号： H01L29/792 , H01L27/11556 , H01L27/11582
摘要： According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.
摘要翻译：根据本发明构思的示例实施例，非易失性存储器件包括：衬底，其包括与第一杂质区交叉的第二杂质区，以及在衬底上沿垂直方向延伸的沟道区。栅电极可以沿着沟道区域的外壁在垂直方向和水平方向上彼此分离。第一绝缘中间层可以在栅电极和沟道区上，其中第一绝缘中间层限定了至少一个相邻的栅电极之间的接触孔和接触孔，以形成与第二杂质电连接的接触孔地区。蚀刻停止层图案可以在接触插塞和第一绝缘中间层上。

4. 发明申请

US20130214344A1 NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20130214344A1
公开(公告)日：2013-08-22
申请号：US13668854
申请日：2012-11-05
申请人： Jong-heun Lim , Ki-ho Bae , Hyo-jung Kim , Kyung-hyun Kim , Chan-wook Seo , Young-beom Pyon
发明人： Jong-heun Lim , Ki-ho Bae , Hyo-jung Kim , Kyung-hyun Kim , Chan-wook Seo , Young-beom Pyon
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11556 , H01L27/11582
摘要： According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.
摘要翻译：根据本发明构思的示例实施例，非易失性存储器件包括：衬底，其包括与第一杂质区交叉的第二杂质区，以及在衬底上沿垂直方向延伸的沟道区。栅电极可以沿着沟道区域的外壁在垂直方向和水平方向上彼此分离。第一绝缘中间层可以在栅电极和沟道区上，其中第一绝缘中间层限定了至少一个相邻的栅电极之间的接触孔和接触孔，以形成与第二杂质电连接的接触孔地区。蚀刻停止层图案可以在接触插塞和第一绝缘中间层上。

5. 发明申请

US20100093165A1 Method of fabricating integrated circuit semiconductor device having gate metal silicide layer 审中-公开
标题翻译：制造具有栅极金属硅化物层的集成电路半导体器件的方法
公开(公告)号：US20100093165A1
公开(公告)日：2010-04-15
申请号：US12453866
申请日：2009-05-26
申请人： Ki-ho Bae , Kwang-bok Kim , Choong-kee Seong , In-seak Hwang , Ki-jong Park , Kyung-hyun Kim
发明人： Ki-ho Bae , Kwang-bok Kim , Choong-kee Seong , In-seak Hwang , Ki-jong Park , Kyung-hyun Kim
IPC分类号： H01L21/8234 , H01L21/306
CPC分类号： H01L27/11519 , H01L21/0334 , H01L27/11521
摘要： Provided is a method of fabricating an integrated circuit semiconductor device. The method may include forming a plurality of gate patterns spaced apart from each other on a semiconductor substrate, the plurality of gate patterns including gate electrodes and gate capping patterns. After an interlayer insulating layer is formed to insulate the gate patterns, the interlayer insulating layer and the gate capping patterns may be planarized by etching until top surfaces of the gate electrodes are exposed. Gate metal silicide layers may be selectively formed on the gate electrodes.
摘要翻译：提供一种制造集成电路半导体器件的方法。所述方法可以包括在半导体衬底上形成彼此间隔开的多个栅极图案，所述多个栅极图案包括栅电极和栅极封盖图案。在形成层间绝缘层以使栅极图案绝缘之后，可以通过蚀刻来平坦化层间绝缘层和栅极封盖图案，直到栅电极的顶表面露出。可以在栅电极上选择性地形成栅极金属硅化物层。

6. 发明申请

US20050266647A1 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20050266647A1
公开(公告)日：2005-12-01
申请号：US11082616
申请日：2005-03-17
申请人： Tae-hyun Kim , Byoung-moon Yoon , Won-jun Lee , Yong-sun Ko , Kyung-hyun Kim
发明人： Tae-hyun Kim , Byoung-moon Yoon , Won-jun Lee , Yong-sun Ko , Kyung-hyun Kim
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： Methods of manufacturing a semiconductor device are provided. A trench is formed in a semiconductor substrate. A first field oxide layer is formed that partially fills the trench. The first field oxide layer defines an active region of the substrate that is adjacent to the trench. An upper portion of sidewalls of the trench extends upward beyond a surface of the first field oxide layer. A first liner is formed on the first field oxide layer and on the portion of the sidewalls of the trench that extend upward beyond the first field oxide layer. A second field oxide layer is formed on the first liner and fills the trench. The second field oxide layer and the first liner are each partially removed to expose a top adjacent surface and upper sidewalls of the trench along the active region of the substrate. A dielectric layer is formed on the exposed top adjacent surface and upper sidewalls of the trench. A gate electrode is formed on the dielectric layer.
摘要翻译：提供制造半导体器件的方法。在半导体衬底中形成沟槽。形成部分填充沟槽的第一场氧化物层。第一场氧化物层限定与沟槽相邻的衬底的有源区。沟槽的侧壁的上部向上延伸超过第一场氧化物层的表面。第一衬垫形成在第一场氧化物层上并且在沟槽的侧壁的部分上方向上延伸超过第一场氧化物层。在第一衬垫上形成第二场氧化物层并填充沟槽。每个部分去除第二场氧化物层和第一衬里以沿着衬底的有源区域暴露沟槽的顶部相邻表面和上侧壁。介电层形成在沟槽的暴露的顶部相邻表面和上侧壁上。在电介质层上形成栅电极。

7. 发明授权

US07151043B2 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07151043B2
公开(公告)日：2006-12-19
申请号：US11082616
申请日：2005-03-17
申请人： Tae-hyun Kim , Byoung-moon Yoon , Won-jun Lee , Yong-sun Ko , Kyung-hyun Kim
发明人： Tae-hyun Kim , Byoung-moon Yoon , Won-jun Lee , Yong-sun Ko , Kyung-hyun Kim
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： Methods of manufacturing a semiconductor device are provided. A trench is formed in a semiconductor substrate. A first field oxide layer is formed that partially fills the trench. The first field oxide layer defines an active region of the substrate that is adjacent to the trench. An upper portion of sidewalls of the trench extends upward beyond a surface of the first field oxide layer. A first liner is formed on the first field oxide layer and on the portion of the sidewalls of the trench that extend upward beyond the first field oxide layer. A second field oxide layer is formed on the first liner and fills the trench. The second field oxide layer and the first liner are each partially removed to expose a top adjacent surface and upper sidewalls of the trench along the active region of the substrate. A dielectric layer is formed on the exposed top adjacent surface and upper sidewalls of the trench. A gate electrode is formed on the dielectric layer.
摘要翻译：提供制造半导体器件的方法。在半导体衬底中形成沟槽。形成部分填充沟槽的第一场氧化物层。第一场氧化物层限定与沟槽相邻的衬底的有源区。沟槽的侧壁的上部向上延伸超过第一场氧化物层的表面。第一衬垫形成在第一场氧化物层上并且在沟槽的侧壁的部分上方向上延伸超过第一场氧化物层。在第一衬垫上形成第二场氧化物层并填充沟槽。每个部分去除第二场氧化物层和第一衬里以沿着衬底的有源区域暴露沟槽的顶部相邻表面和上侧壁。介电层形成在沟槽的暴露的顶部相邻表面和上侧壁上。在电介质层上形成栅电极。

8. 发明授权

US08321777B2 Cyclic redundancy check code generating circuit, semiconductor memory device, and method of driving semiconductor memory device 有权
标题翻译：循环冗余校验码产生电路，半导体存储器件以及驱动半导体存储器件的方法
公开(公告)号：US08321777B2
公开(公告)日：2012-11-27
申请号：US12002557
申请日：2007-12-18
申请人： Kyung-hyun Kim
发明人： Kyung-hyun Kim
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/09 , G06F11/1004 , H03M13/1102 , H03M13/136 , H03M13/1515 , H03M13/19 , H03M13/2957
摘要： Disclosed are a semiconductor memory device, and a method of driving the same, and a cyclic redundancy check code generating circuit capable of performing cyclic redundancy check. A semiconductor memory device according to an aspect of the present invention includes a memory cell array, a data processing unit receiving data that is read from the memory cell array and selectively outputting at least some of the data according to ordering information, bit structure information, and burst length information, and a check code generating unit generating a cyclic redundancy check code to detect an error in the data being output, the check code generating unit generating and outputting the cyclic redundancy check code by using the read data, the ordering information, the bit structure information, and the burst length information.
摘要翻译：公开了一种半导体存储器件及其驱动方法，以及能够执行循环冗余校验的循环冗余校验码产生电路。根据本发明的一个方面的半导体存储器件包括存储单元阵列，数据处理单元，接收从存储单元阵列读取的数据，并根据排序信息，比特结构信息选择性地输出数据中的至少一些，检测码生成部，生成循环冗余校验码，检测出正在输出的数据的错误;校验码生成部，使用读取的数据生成并输出循环冗余校验码，排序信息，比特结构信息和突发长度信息。

9. 发明申请

US20070155178A1 Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same 审中-公开
标题翻译：用于化学机械抛光工艺的浆料及使用其制造半导体器件的方法
公开(公告)号：US20070155178A1
公开(公告)日：2007-07-05
申请号：US11712931
申请日：2007-03-01
申请人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phill Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
发明人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phill Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
IPC分类号： H01L21/306 , H01L21/461 , B44C1/22 , C23F1/00 , H01L21/302
CPC分类号： H01L21/76224 , B24B37/044 , C09G1/02 , H01L21/31053
摘要： A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.
摘要翻译：公开了一种用于材料层表面例如氧化硅层的化学机械抛光的浆料组合物。暴露于浆料的第一材料表面显示出亲水性，而第二材料层，例如其表面也暴露于浆料的多晶硅层，表现出疏水性，因此用作抛光停止层。浆料组合物基本上由水，磨料颗粒和具有亲水和疏水官能团的聚合物添加剂组成。

10. 发明授权

US06626968B2 Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same 失效
公开(公告)号：US06626968B2
公开(公告)日：2003-09-30
申请号：US09861697
申请日：2001-05-21
申请人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phil Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
发明人： Young-rae Park , Jung-yup Kim , Bo-un Yoon , Kwang-bok Kim , Jae-phil Boo , Jong-won Lee , Sang-rok Hah , Kyung-hyun Kim , Chang-ki Hong
IPC分类号： C09G102
CPC分类号： H01L21/76224 , B24B37/044 , C09G1/02 , H01L21/31053
摘要： A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

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