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1. 发明申请

US20110273950A1 Method and apparatus for programming an anti-fuse element in a high-voltage integrated circuit 有权
标题翻译：用于在高压集成电路中编程抗熔丝元件的方法和装置
公开(公告)号：US20110273950A1
公开(公告)日：2011-11-10
申请号：US12800095
申请日：2010-05-07
申请人： Sujit Banerjee , Giao Minh Pham
发明人： Sujit Banerjee , Giao Minh Pham
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： A method for programming a programmable block of a power IC device includes selecting an anti-fuse element of the programmable block to be programmed. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to a pin of the power IC device. The pin is connected to a drain of a high-voltage field-effect transistor (HVFET) that drives an external load via the pin during a normal operating mode of the power IC device. The voltage pulse, which is coupled to the first capacitive plate of the anti-fuse element, has a potential sufficiently high to cause a current to flow through the anti-fuse element that destroys at least a portion of the dielectric layer, thereby electrically shorting the first and second capacitive plates
摘要翻译：用于对功率IC器件的可编程块进行编程的方法包括选择要编程的可编程块的反熔丝元件。反熔丝元件包括由电介质层分隔开的第一和第二电容板。然后将电压脉冲施加到功率IC器件的引脚。该引脚连接到高电压场效应晶体管（HVFET）的漏极，在功率IC器件的正常工作模式下通过引脚驱动外部负载。耦合到抗熔丝元件的第一电容板的电压脉冲具有足够高的电位，使电流流过反熔丝元件，破坏电介质层的至少一部分，由此电短路第一和第二电容板

2. 发明授权

US07932738B1 Method and apparatus for reading a programmable anti-fuse element in a high-voltage integrated circuit 有权
标题翻译：用于读取高压集成电路中的可编程反熔丝元件的方法和装置
公开(公告)号：US07932738B1
公开(公告)日：2011-04-26
申请号：US12800054
申请日：2010-05-07
申请人： Sujit Banerjee , Giao Minh Pham
发明人： Sujit Banerjee , Giao Minh Pham
IPC分类号： G01R31/02
CPC分类号： G01R31/2601 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： In a method for reading a programmable anti-fuse block of a high-voltage integrated circuit a first voltage is applied to a first pin of the HVIC, the first voltage being lowered to a second voltage at a first node. Current is shunted from the first node, thereby lowering the second voltage to a third voltage. An isolation circuit block is then activated to couple the third voltage to a common node of the programmable anti-fuse block, the common node being coupled to a plurality of anti-fuses, each anti-fuse having a programmed state. A read signal is generated that causes a voltage potential representative of the programmed state of each anti-fuse to be latched into a corresponding latch element.
摘要翻译：在用于读取高压集成电路的可编程反熔丝块的方法中，第一电压施加到HVIC的第一引脚，第一电压降低到第一节点处的第二电压。电流从第一节点分流，从而将第二电压降低到第三电压。然后激活隔离电路块以将第三电压耦合到可编程反熔丝块的公共节点，公共节点耦合到多个抗熔丝，每个反熔丝具有编程状态。产生一个读出信号，使得表示每个反熔丝的编程状态的电压电位被锁存在相应的锁存元件中。

3. 发明申请

US20110276292A1 Method and apparatus for reading a programmable anti-fuse element in a high-voltage integrated circuit 有权
公开(公告)号：US20110276292A1
公开(公告)日：2011-11-10
申请号：US13066624
申请日：2011-04-20
申请人： Sujit Banerjee , Giao Minh Pham
发明人： Sujit Banerjee , Giao Minh Pham
IPC分类号： G06F19/00
CPC分类号： G01R31/2601 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： In a method for reading a programmable anti-fuse block of a high-voltage integrated circuit a first voltage is applied to a first pin of the HVIC, the first voltage being lowered to a second voltage at a first node. Current is shunted from the first node, thereby lowering the second voltage to a third voltage. An isolation circuit block is then activated to couple the third voltage to a common node of the programmable anti-fuse block, the common node being coupled to a plurality of anti-fuses, each anti-fuse having a programmed state. A read signal is generated that causes a voltage potential representative of the programmed state of each anti-fuse to be latched into a corresponding latch element.

4. 发明授权

US08487646B2 Method and apparatus for reading a programmable anti-fuse element in a high-voltage integrated circuit 有权
标题翻译：用于读取高压集成电路中的可编程反熔丝元件的方法和装置
公开(公告)号：US08487646B2
公开(公告)日：2013-07-16
申请号：US13066624
申请日：2011-04-20
申请人： Sujit Banerjee , Giao Minh Pham
发明人： Sujit Banerjee , Giao Minh Pham
IPC分类号： G01R31/02
CPC分类号： G01R31/2601 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： In a method for reading a programmable anti-fuse block of a high-voltage integrated circuit a first voltage is applied to a first pin of the HVIC, the first voltage being lowered to a second voltage at a first node. Current is shunted from the first node, thereby lowering the second voltage to a third voltage. An isolation circuit block is then activated to couple the third voltage to a common node of the programmable anti-fuse block, the common node being coupled to a plurality of anti-fuses, each anti-fuse having a programmed state. A read signal is generated that causes a voltage potential representative of the programmed state of each anti-fuse to be latched into a corresponding latch element.
摘要翻译：在用于读取高压集成电路的可编程反熔丝块的方法中，第一电压施加到HVIC的第一引脚，第一电压降低到第一节点处的第二电压。电流从第一节点分流，从而将第二电压降低到第三电压。然后激活隔离电路块以将第三电压耦合到可编程反熔丝块的公共节点，公共节点耦合到多个抗熔丝，每个反熔丝具有编程状态。产生一个读出信号，使得表示每个反熔丝的编程状态的电压电位被锁存在相应的锁存元件中。

5. 发明授权

US08305826B2 Method and apparatus for programming an anti-fuse element in a high-voltage integrated circuit 有权
标题翻译：用于在高压集成电路中编程抗熔丝元件的方法和装置
公开(公告)号：US08305826B2
公开(公告)日：2012-11-06
申请号：US12800095
申请日：2010-05-07
申请人： Sujit Banerjee , Giao Minh Pham
发明人： Sujit Banerjee , Giao Minh Pham
IPC分类号： G11C17/00 , G11C17/18
CPC分类号： G11C17/16
摘要： A method for programming a programmable block of a power IC device includes selecting an anti-fuse element of the programmable block to be programmed. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to a pin of the power IC device. The pin is connected to a drain of a high-voltage field-effect transistor (HVFET) that drives an external load via the pin during a normal operating mode of the power IC device. The voltage pulse, which is coupled to the first capacitive plate of the anti-fuse element, has a potential sufficiently high to cause a current to flow through the anti-fuse element that destroys at least a portion of the dielectric layer, thereby electrically shorting the first and second capacitive plates.
摘要翻译：用于对功率IC器件的可编程块进行编程的方法包括选择要编程的可编程块的反熔丝元件。反熔丝元件包括由电介质层分隔开的第一和第二电容板。然后将电压脉冲施加到功率IC器件的引脚。该引脚连接到高电压场效应晶体管（HVFET）的漏极，该电压在电源IC器件的正常工作模式期间通过引脚驱动外部负载。耦合到抗熔丝元件的第一电容板的电压脉冲具有足够高的电位，使电流流过反熔丝元件，破坏电介质层的至少一部分，由此电短路第一和第二电容板。

6. 发明申请

US20120273885A1 High-Voltage Transistor Structure with Reduced Gate Capacitance 有权
标题翻译：具有降低栅极电容的高压晶体管结构
公开(公告)号：US20120273885A1
公开(公告)日：2012-11-01
申请号：US13532583
申请日：2012-06-25
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/0882 , H01L29/42368
摘要： In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.
摘要翻译：在一个实施例中，高电压场效应晶体管（HVFET）包括覆盖第一阱区的场氧化物层，所述场氧化物层具有第一厚度并且在第二横向方向上从漏极区延伸到接近第二阱地区。栅极氧化物覆盖沟道区域并且具有在第一横向方向上的第二尺寸。栅极在第二横向方向上从源极区域延伸到场氧化物层的一部分，栅极通过栅极氧化物与沟道区域绝缘，栅极在第一横向尺寸上延伸超过HVFET的非有效区域超过栅极氧化物的第二维度，栅极通过场氧化物层与无源区域上的第一和第二阱区绝缘。

7. 发明申请

US20120146105A1 High-voltage transistor device with integrated resistor 有权
标题翻译：具有集成电阻的高压晶体管器件
公开(公告)号：US20120146105A1
公开(公告)日：2012-06-14
申请号：US13385264
申请日：2012-02-10
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L27/06
CPC分类号： H01L29/808 , H01L27/0629 , H01L28/20 , H01L29/0634 , H01L29/1058 , H01L29/1066
摘要： A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：高压器件结构包括耦合到抽头晶体管的电阻器，其包括JFET，其中当外部电压小于钳位电压时，在JFET的端子处提供的电压基本上与外部电压成比例的JFET。当外部电压大于夹断电压时，端子处提供的电压基本上恒定。当外部电压大于夹断电压时，电阻器的一端基本上处于外部电压。当外部电压为负时，电阻限制注入基板的电流。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。

8. 发明申请

US20120061755A1 Checkerboarded high-voltage vertical transistor layout 失效
标题翻译：棋盘式高压立式晶体管布局
公开(公告)号：US20120061755A1
公开(公告)日：2012-03-15
申请号：US13199792
申请日：2011-09-09
申请人： Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
发明人： Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
IPC分类号： H01L29/78
CPC分类号： H01L27/0211 , H01L27/0207 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7811 , H01L29/7813
摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分和设置在邻近第一区域的半导体管芯的第二区域中的晶体管段的第二部分。第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱。第一和第二电介质区域设置在柱的相对侧上。第一和第二场板分别设置在第一和第二电介质区域中。邻接第一和第二部分的晶体管段的外场板被分离或部分合并。

9. 发明申请

US20110140166A1 Method of fabricating a deep trench insulated gate bipolar transistor 失效
公开(公告)号：US20110140166A1
公开(公告)日：2011-06-16
申请号：US12930626
申请日：2011-01-11
申请人： Vijay Parthasarathy , Sujit Banerjee
发明人： Vijay Parthasarathy , Sujit Banerjee
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/66333
摘要： In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.

10. 发明申请

US20110042726A1 High-voltage transistor device with integrated resistor 有权
标题翻译：具有集成电阻的高压晶体管器件
公开(公告)号：US20110042726A1
公开(公告)日：2011-02-24
申请号：US12583426
申请日：2009-08-20
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L29/80 , H01L27/105
CPC分类号： H01L29/808 , H01L27/0629 , H01L28/20 , H01L29/0634 , H01L29/1058 , H01L29/1066
摘要： A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：高压器件结构包括耦合到抽头晶体管的电阻器，其包括JFET，其中当外部电压小于钳位电压时，JFET端子处的电压基本上与外部电压成比例的JFET。当外部电压大于夹断电压时，端子处提供的电压基本上恒定。当外部电压大于夹断电压时，电阻器的一端基本上处于外部电压。当外部电压为负时，电阻限制注入基板的电流。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

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