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    • 1. 发明申请
      US20110252393A1 AUTOMATIC GENERATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRCUITS 有权
    • AUTOMATIC GENERATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRCUITS
    • 用于电子电路的合并模式约束的自动生成
    • US20110252393A1
    • 2011-10-13
    • US12960745
    • 2010-12-06
    • Subramanyam Sripada , Sonia Singhal , Cho Moon
    • Subramanyam Sripada , Sonia Singhal , Cho Moon
    • G06F17/50
    • G06F17/5031
    • Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes.
    • 与一组网表相关联的单独模式时序约束被组合成合并模式时序约束。 通过组合来自各个模式的时序约束产生初始合并模式约束。 初始合并模式包括来自各个模式的所有时序约束的并集，这些模式添加了时序关系以及来自消除时序关系的各个模式的所有时序约束的交集。 在合并模式中识别出外部定时关系，并通过在合并模式中引入时序约束来消除。 通过将合并模式中的时间关系与各模式中的时间关系进行比较来验证合并模式和各模式之间的等效性。 如果在合并模式中存在各个模式中存在的每个定时关系，并且以合并模式存在的每个定时关系存在于各个模式中的任一个中，则将合并模式视为等同于各个模式。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明申请
      US20110252390A1 AUTOMATIC VERIFICATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRCUITS 有权
    • AUTOMATIC VERIFICATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRCUITS
    • 用于电子电路的合并模式约束的自动验证
    • US20110252390A1
    • 2011-10-13
    • US13025075
    • 2011-02-10
    • Subramanyam Sripada , Sonia Singhal , Cho Moon
    • Subramanyam Sripada , Sonia Singhal , Cho Moon
    • G06F17/50
    • G06F17/5022
    • Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes.
    • 与一组网表相关联的单独模式时序约束被组合成合并模式时序约束。 通过组合来自各个模式的时序约束产生初始合并模式约束。 初始合并模式包括来自各个模式的所有时序约束的并集，这些模式添加了时序关系以及来自消除时序关系的各个模式的所有时序约束的交集。 在合并模式中识别出外部定时关系，并通过在合并模式中引入时序约束来消除。 通过将合并模式中的时间关系与各模式中的时间关系进行比较来验证合并模式和各模式之间的等效性。 如果在合并模式中存在各个模式存在的每个定时关系，并且合并模式中存在的每个定时关系存在于各种模式中的任何一种中，则将合并模式视为等同于各个模式。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US08627262B2 Automatic generation of merged mode constraints for electronic circuits 有权
    • Automatic generation of merged mode constraints for electronic circuits
    • 自动生成电子电路的合并模式约束
    • US08627262B2
    • 2014-01-07
    • US12960745
    • 2010-12-06
    • Subramanyam Sripada , Sonia Singhal , Cho Moon
    • Subramanyam Sripada , Sonia Singhal , Cho Moon
    • G06F17/50
    • G06F17/5031
    • Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes.
    • 与一组网表相关联的单独模式时序约束被组合成合并模式时序约束。 通过组合来自各个模式的时序约束产生初始合并模式约束。 初始合并模式包括来自各个模式的所有时序约束的并集，这些模式添加了时序关系以及来自消除时序关系的各个模式的所有时序约束的交集。 在合并模式中识别出外部定时关系，并通过在合并模式中引入时序约束来消除。 通过将合并模式中的时间关系与各模式中的时间关系进行比较来验证合并模式和各模式之间的等效性。 如果在合并模式中存在各个模式存在的每个定时关系，并且合并模式中存在的每个定时关系存在于各种模式中的任何一种中，则将合并模式视为等同于各个模式。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US08607186B2 Automatic verification of merged mode constraints for electronic circuits 有权
    • Automatic verification of merged mode constraints for electronic circuits
    • 自动验证电子电路的合并模式约束
    • US08607186B2
    • 2013-12-10
    • US13025075
    • 2011-02-10
    • Subramanyam Sripada , Sonia Singhal , Cho Moon
    • Subramanyam Sripada , Sonia Singhal , Cho Moon
    • G06F17/50 , G06F9/455
    • G06F17/5022
    • Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes.
    • 与一组网表相关联的单独模式时序约束被组合成合并模式时序约束。 通过组合来自各个模式的时序约束产生初始合并模式约束。 初始合并模式包括来自各个模式的所有时序约束的并集，这些模式添加了时序关系以及来自消除时序关系的各个模式的所有时序约束的交集。 在合并模式中识别出外部定时关系，并通过在合并模式中引入时序约束来消除。 通过将合并模式中的时间关系与各模式中的时间关系进行比较来验证合并模式和各模式之间的等效性。 如果在合并模式中存在各个模式中存在的每个定时关系，并且以合并模式存在的每个定时关系存在于各个模式中的任一个中，则将合并模式视为等同于各个模式。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US08261221B2 Comparing timing constraints of circuits 有权
    • Comparing timing constraints of circuits
    • 比较电路的时序约束
    • US08261221B2
    • 2012-09-04
    • US12759625
    • 2010-04-13
    • Sonia Singhal , Loa Mize , Cho Moon
    • Sonia Singhal , Loa Mize , Cho Moon
    • G06F17/50 , G06F9/455
    • G06F17/5031 , G06F2217/84
    • Timing behaviors associated with constraints of circuits are compared to identify mismatches between circuit configurations. Aggregate sets of timing constraints associated with timing nodes are determined for timing paths between start points and end points. Precedence rules are applied to aggregate sets of timing constraints by applying precedence rules to interacting timing constraints. Aggregate sets of constraints for corresponding timing nodes are matched to determine if timing constraint mismatches exist between circuits. If aggregate timing constraints associated with start point, end point pairs are found to match, reconvergent points between the start point and end points are analyzed to see if aggregate constraints of timing nodes connected to reconvergent/divergent points match if timing exception matches are involved. Graph traversal algorithms allow efficient computation of aggregate timing constraints for timing nodes.
    • 比较与电路约束相关的定时行为，以识别电路配置之间的不匹配。 与起始点和终点之间的定时路径确定与定时节点相关联的时间约束集合。 优先规则通过将优先规则应用于交互时序约束来应用于聚合时间约束集合。 匹配相应定时节点的约束集合，以确定电路之间是否存在时序约束不匹配。 如果发现与起始点，终点对相关联的聚合时序约束匹配，则分析起始点和终点之间的重新收敛点，以查看连接到再次收敛/发散点的定时节点的聚合约束是否涉及定时异常匹配。 图形遍历算法可以有效计算定时节点的聚合时序约束。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明申请
      US20110252388A1 COMPARING TIMING CONSTRAINTS OF CIRCUITS 有权
    • COMPARING TIMING CONSTRAINTS OF CIRCUITS
    • 比较电路的时序约束
    • US20110252388A1
    • 2011-10-13
    • US12759625
    • 2010-04-13
    • Sonia Singhal , Loa Mize , Cho Moon
    • Sonia Singhal , Loa Mize , Cho Moon
    • G06F17/50
    • G06F17/5031 , G06F2217/84
    • Timing behaviors associated with constraints of circuits are compared to identify mismatches between circuit configurations. Aggregate sets of timing constraints associated with timing nodes are determined for timing paths between start points and end points. Precedence rules are applied to aggregate sets of timing constraints by applying precedence rules to interacting timing constraints. Aggregate sets of constraints for corresponding timing nodes are matched to determine if timing constraint mismatches exist between circuits. If aggregate timing constraints associated with start point, end point pairs are found to match, reconvergent points between the start point and end points are analyzed to see if aggregate constraints of timing nodes connected to reconvergent/divergent points match if timing exception matches are involved. Graph traversal algorithms allow efficient computation of aggregate timing constraints for timing nodes.
    • 比较与电路约束相关的定时行为，以识别电路配置之间的不匹配。 与起始点和终点之间的定时路径确定与定时节点相关联的时间约束集合。 优先规则通过将优先规则应用于交互时序约束来应用于聚合时间约束集合。 匹配相应定时节点的约束集合，以确定电路之间是否存在时序约束不匹配。 如果发现与起始点，终点对相关联的聚合时序约束匹配，则分析起始点和终点之间的重新收敛点，以查看连接到再次收敛/发散点的定时节点的聚合约束是否涉及定时异常匹配。 图形遍历算法可以有效计算定时节点的聚合时序约束。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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