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1. 发明授权

US08225049B2 Data storage device having self-powered semiconductor device 有权
标题翻译：具有自供电半导体器件的数据存储装置
公开(公告)号：US08225049B2
公开(公告)日：2012-07-17
申请号：US12689317
申请日：2010-01-19
申请人： Subramanya Mayya , Hee-seok Kim , Ik-Soo Kim , Min-Young Park , Hyun-Suk Kwon
发明人： Subramanya Mayya , Hee-seok Kim , Ik-Soo Kim , Min-Young Park , Hyun-Suk Kwon
IPC分类号： G06F13/16
CPC分类号： H01L27/10897 , H01L23/58 , H01L25/0657 , H01L25/16 , H01L27/10876 , H01L27/10894 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2924/0002 , H01L2924/00
摘要： Provided is a data storage device. The data storage device includes an interface, a buffer controller, a memory controller, a non-volatile memory, and a self-powered semiconductor device adjacent to and electrically connected to the buffer controller. The self-powered semiconductor device includes a semiconductor chip and a rechargeable micro-battery attached to the semiconductor chip. The rechargeable micro-battery includes a first current collector and a second current collector, which face each other, a first polarizing electrode in contact with the first current collector and facing the second current collector, a second polarizing electrode in contact with the second current collector and facing the first polarizing electrode, and an electrolyte layer formed between the first and second polarizing electrodes.
摘要翻译：提供了一种数据存储装置。数据存储设备包括接口，缓冲器控制器，存储器控制器，非易失性存储器以及与缓冲器控制器相邻并电连接的自供电半导体器件。自供电的半导体器件包括半导体芯片和附接到半导体芯片的可再充电微型电池。所述可再充电微电池包括彼此面对的第一集电体和第二集电体，与所述第一集电体接触并面对所述第二集电体的第一极化电极，与所述第二集电体接触的第二极化电极，并且面对第一极化电极，以及形成在第一和第二极化电极之间的电解质层。

2. 发明授权

US08871559B2 Methods for fabricating phase change memory devices 有权
标题翻译：制造相变存储器件的方法
公开(公告)号：US08871559B2
公开(公告)日：2014-10-28
申请号：US13154631
申请日：2011-06-07
申请人： Hideki Horii , Hyun-Suk Kwon , Hyeyoung Park
发明人： Hideki Horii , Hyun-Suk Kwon , Hyeyoung Park
IPC分类号： H01L21/00 , H01L45/00 , H01L27/24
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： Provided is a method for fabricating a phase change memory device. The method includes forming a plurality of bottom electrodes on a substrate, forming a first mold layer on the substrate to extend in a first direction where the bottom electrodes are exposed, forming a second mold layer on the substrate, the second mold layer extending in a second direction orthogonal to the first direction to expose parts of the bottom electrodes, forming a phase change material layer on the first and second mold layers to be connected to parts of the bottom electrodes dividing the phase change material layer as a plurality of phase change layers respectively connected to the parts of the bottom electrodes and forming a plurality of top electrodes on the phase change layers.
摘要翻译：提供了一种制造相变存储器件的方法。该方法包括在基板上形成多个底部电极，在基板上形成第一模具层，以在底部电极暴露的第一方向上延伸，在基板上形成第二模具层，第二模具层与所述第一方向正交的第二方向以暴露所述底部电极的部分，在所述第一和第二模具层上形成相变材料层，以连接到将相变材料层划分为多个相变层的底部电极的部分分别连接到底部电极的部分并在相变层上形成多个顶部电极。

3. 发明申请

US20110186798A1 Phase Changeable Memory Devices and Methods of Forming the Same 审中-公开
标题翻译：相变存储器件及其形成方法
公开(公告)号：US20110186798A1
公开(公告)日：2011-08-04
申请号：US13019822
申请日：2011-02-02
申请人： Hyun-Suk Kwon , Hyeyoung Park , Jeonghee Park , Gyuhwan Oh , Jinho Oh , Doo-Hwan Park
发明人： Hyun-Suk Kwon , Hyeyoung Park , Jeonghee Park , Gyuhwan Oh , Jinho Oh , Doo-Hwan Park
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2463 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/124 , H01L45/1683 , H01L45/1691
摘要： Phase changeable memory devices are provided including a mold insulating layer on a substrate, the mold insulating layer defining an opening therein. A phase-change material layer is provided in the opening. The phase-change material includes an upper surface that is below a surface of the mold insulating layer. A first electrode is provided in the opening and on the phase-change material layer. A spacer is provided between a sidewall of the mold insulating layer and the phase-change material layer and the first electrode. The upper surface of the first electrode is coplanar with the surface of the mold insulating layer. Related methods are also provided.
摘要翻译：提供了相变存储器件，其包括在基底上的模具绝缘层，模具绝缘层在其中限定开口。在开口中设置相变材料层。相变材料包括在模具绝缘层的表面下方的上表面。第一电极设置在开口和相变材料层上。在模具绝缘层的侧壁和相变材料层和第一电极之间设置间隔件。第一电极的上表面与模具绝缘层的表面共面。还提供了相关方法。

4. 发明申请

US20090250682A1 PHASE CHANGE MEMORY DEVICE 审中-公开
标题翻译：相变存储器件
公开(公告)号：US20090250682A1
公开(公告)日：2009-10-08
申请号：US12406344
申请日：2009-03-18
申请人： Doo-Hwan Park , Yong-Ho Ha , Myung-Jin Kang , Jeong-Hee Park , Hyun-Suk Kwon
发明人： Doo-Hwan Park , Yong-Ho Ha , Myung-Jin Kang , Jeong-Hee Park , Hyun-Suk Kwon
IPC分类号： H01L45/00
CPC分类号： H01L45/143 , G11C13/0004 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1666 , H01L45/1683
摘要： Provided is a phase change memory device. The phase change memory device includes a first electrode and a second electrode. A phase change material pattern is interposed between the first and second electrodes. A phase change auxiliary pattern is in contact with at least one side of the phase change material pattern. The phase change auxiliary pattern includes a compound having a chemical formula expressed as DaMb[GxTy]c(0≦a/(a+b+c)≦0.2, 0≦b/(a+b+c)≦0.1, 0.3≦x/(x+y)≦0.7), where D comprises: at least one of C, N, and O; M comprises at least one of a transition metal, Al, Ga, and In; G comprises Ge; and T comprises Te.
摘要翻译：提供了一种相变存储器件。相变存储器件包括第一电极和第二电极。相变材料图案插入在第一和第二电极之间。相变辅助图案与相变材料图案的至少一侧接触。相变辅助图案包括化学式表示为DaMb [GxTy] c（0 <= a /（a + b + c）<= 0.2,0 <= b /（a + b + c） 0.1，0.3 <= x /（x + y）≤= 0.7），其中D包括：C，N和O中的至少一个; M包括过渡金属Al，Ga和In中的至少一种; G包括Ge; T包括Te。

5. 发明申请

US20120068136A1 Phase Change Memory Device, Storage System Having the Same and Fabricating Method Thereof 有权
标题翻译：相变存储器件，具有相同的存储系统及其制造方法
公开(公告)号：US20120068136A1
公开(公告)日：2012-03-22
申请号：US13234924
申请日：2011-09-16
申请人： Hye-Young Park , Jeong-Hee Park , Hyun-Suk Kwon
发明人： Hye-Young Park , Jeong-Hee Park , Hyun-Suk Kwon
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/124 , H01L45/1293 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： Provided are a phase change memory device and a fabricating method thereof. The phase change memory device includes a substrate, an interlayer dielectric layer formed on the substrate, first and second contact holes formed in the interlayer dielectric layer, and a memory cell formed in the first and second contact holes and including a diode, a first electrode on the diode, a phase change material layer on the first electrode, and a second electrode on the phase change material layer, wherein the first contact hole and the second contact hole are spaced apart from and separated from each other.
摘要翻译：提供了一种相变存储器件及其制造方法。相变存储器件包括衬底，形成在衬底上的层间电介质层，形成在层间电介质层中的第一和第二接触孔以及形成在第一和第二接触孔中并包括二极管的存储单元，第二电极在所述二极管上，所述第一电极上的相变材料层和所述相变材料层上的第二电极，其中所述第一接触孔和所述第二接触孔彼此间隔开并且彼此分离。

6. 发明申请

US20110147692A1 VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：可变电阻记忆体装置及其形成方法
公开(公告)号：US20110147692A1
公开(公告)日：2011-06-23
申请号：US12973124
申请日：2010-12-20
申请人： JEONGHEE PARK , Hideki Horii , Hyeyoung Park , Jin Ho Oh , Hyun-Suk Kwon
发明人： JEONGHEE PARK , Hideki Horii , Hyeyoung Park , Jin Ho Oh , Hyun-Suk Kwon
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/1293 , H01L45/141 , H01L45/1683
摘要： Provided are a variable resistance memory device and a method of forming the same. The variable resistance memory device may include a substrate, a plurality of bottom electrodes on the substrate, and a first interlayer insulating layer including a trench formed therein. The trench exposes the bottom electrodes and extends in a first direction. The variable resistance memory device further includes a top electrode provided on the first interlayer insulating layer and extending in a second direction crossing the first direction and a plurality of variable resistance patterns provided in the trench and having sidewalls aligned with a sidewall of the top electrode.
摘要翻译：提供了一种可变电阻存储器件及其形成方法。可变电阻存储器件可以包括衬底，在衬底上的多个底部电极，以及包括形成在其中的沟槽的第一层间绝缘层。沟槽露出底部电极并沿第一方向延伸。可变电阻存储器件还包括设置在第一层间绝缘层上并沿与第一方向交叉的第二方向延伸的顶电极和设置在沟槽中并具有与顶电极的侧壁对准的侧壁的多个可变电阻图案。

7. 发明授权

US08552412B2 Variable resistance memory device and method of forming the same 有权
公开(公告)号：US08552412B2
公开(公告)日：2013-10-08
申请号：US12973124
申请日：2010-12-20
申请人： Jeonghee Park , Hideki Horii , Hyeyoung Park , Jin Ho Oh , Hyun-Suk Kwon
发明人： Jeonghee Park , Hideki Horii , Hyeyoung Park , Jin Ho Oh , Hyun-Suk Kwon
IPC分类号： H01L45/00
CPC分类号： H01L45/16 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/1293 , H01L45/141 , H01L45/1683
摘要： Provided are a variable resistance memory device and a method of forming the same. The variable resistance memory device may include a substrate, a plurality of bottom electrodes on the substrate, and a first interlayer insulating layer including a trench formed therein. The trench exposes the bottom electrodes and extends in a first direction. The variable resistance memory device further includes a top electrode provided on the first interlayer insulating layer and extending in a second direction crossing the first direction and a plurality of variable resistance patterns provided in the trench and having sidewalls aligned with a sidewall of the top electrode.

8. 发明授权

US08133757B2 Method of manufacturing a phase changeable memory unit having an enhanced structure to reduce a reset current 有权
标题翻译：制造具有增强结构以减少复位电流的相变存储器单元的方法
公开(公告)号：US08133757B2
公开(公告)日：2012-03-13
申请号：US12592816
申请日：2009-12-03
申请人： Hyun-Suk Kwon , Young-Soo Lim , Sung-Un Kwon , Yong-Ho Ha , Jeong-Hee Park , Joon-Sang Park , Myung-Jin Kang , Doo-Hwan Park
发明人： Hyun-Suk Kwon , Young-Soo Lim , Sung-Un Kwon , Yong-Ho Ha , Jeong-Hee Park , Joon-Sang Park , Myung-Jin Kang , Doo-Hwan Park
IPC分类号： H01L29/02
CPC分类号： H01L27/2436 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.
摘要翻译：相变存储单元包括下电极，具有开口的绝缘层间结构，相变材料层和上电极。下电极形成在基板上。绝缘层间结构具有开口并且形成在下电极和基板上。开口露出下电极并且具有向下逐渐减小的宽度。相变材料层填充开口并部分地覆盖绝缘层间结构的上表面。上电极形成在相变材料层上。

9. 发明申请

US20100144135A1 Method of manufacturing a phase changeable memory unit 有权
标题翻译：制造相变存储器单元的方法
公开(公告)号：US20100144135A1
公开(公告)日：2010-06-10
申请号：US12592816
申请日：2009-12-03
申请人： Hyun-Suk Kwon , Young-Soo Lim , Sung-Un Kwon , Yong-Ho Ha , Jeong-Hee Park , Joon-Sang Park , Myung-Jin Kang , Doo-Hwan Park
发明人： Hyun-Suk Kwon , Young-Soo Lim , Sung-Un Kwon , Yong-Ho Ha , Jeong-Hee Park , Joon-Sang Park , Myung-Jin Kang , Doo-Hwan Park
IPC分类号： H01L21/443
CPC分类号： H01L27/2436 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.
摘要翻译：相变存储单元包括下电极，具有开口的绝缘层间结构，相变材料层和上电极。下电极形成在基板上。绝缘层间结构具有开口并且形成在下电极和基板上。开口露出下电极并且具有向下逐渐减小的宽度。相变材料层填充开口并部分地覆盖绝缘层间结构的上表面。上电极形成在相变材料层上。

10. 发明申请

US20100124800A1 VARIABLE RESISTANCE MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：可变电阻存储器件，其制造方法和包括其的存储器系统
公开(公告)号：US20100124800A1
公开(公告)日：2010-05-20
申请号：US12617754
申请日：2009-11-13
申请人： Jeonghee Park , Sunglae Cho , Yongho Ha , Hyun-Suk Kwon
发明人： Jeonghee Park , Sunglae Cho , Yongho Ha , Hyun-Suk Kwon
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： A method of fabricating a variable resistance memory device includes a plasma etching process to remove contaminants from variable resistance material that forms variable resistance elements of the device. Bottom electrodes are formed on a semiconductor substrate. Next, an interlayer dielectric layer having trenches that expose the bottom electrodes is formed on the substrate. Then a layer of variable resistance material is formed. The variable resistance material covers the interlayer dielectric layer and fills the trenches. The variable resistance material is then planarized down to at least the top surface of the interlayer dielectric layer, thereby leaving elements of the variable resistance material in the trenches. The variable resistance material in the trenches is etched to remove contaminants, produced as a result of the planarizing process, from atop the variable resistance material in the trenches. A top electrode is then formed on the variable resistance material.
摘要翻译：制造可变电阻存储器件的方法包括等离子体蚀刻工艺，以从形成该器件的可变电阻元件的可变电阻材料中除去污染物。底电极形成在半导体衬底上。接下来，在基板上形成具有露出底部电极的沟槽的层间电介质层。然后形成一层可变电阻材料。可变电阻材料覆盖层间电介质层并填充沟槽。然后将可变电阻材料平坦化到至少层间电介质层的顶表面，从而将可变电阻材料的元件留在沟槽中。蚀刻沟槽中的可变电阻材料，以从沟槽中的可变电阻材料的顶部去除作为平坦化处理的结果产生的污染物。然后在可变电阻材料上形成顶部电极。

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