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1. 发明授权

US07484076B1 Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q 有权
标题翻译：执行一次执行Q操作的执行单元上的P操作的SIMD指令（Q
公开(公告)号：US07484076B1
公开(公告)日：2009-01-27
申请号：US11532853
申请日：2006-09-18
申请人： Stuart F. Oberman , Ming Y. Siu , Sameer D. Halepete
发明人： Stuart F. Oberman , Ming Y. Siu , Sameer D. Halepete
IPC分类号： G06F15/80
CPC分类号： G06F9/3869 , G06F9/30105 , G06F9/30109 , G06F9/3012 , G06F9/3836 , G06F9/3851 , G06F9/3875 , G06F9/3887
摘要： Methods, apparatuses, and systems are presented for performing instructions using multiple execution units in a graphics processing unit involving issuing an instruction for P executions of the instruction wherein each execution uses different data, P being a positive integer, the instruction being issued based on a first clock having a first clock rate, operating Q execution units to achieve the P executions of the instruction, Q being a positive integer less than P and greater than one, each of the execution units being operated based on a second clock having a second clock rate higher than the first clock rate of the first clock, and wherein the second clock rate of the second clock is equal to the first clock rate of the first clock multiplied by the ratio P/Q.
摘要翻译：呈现用于在图形处理单元中执行使用多个执行单元的指令的方法，装置和系统，该图形处理单元涉及发出指令的P执行指令，其中每个执行使用不同的数据，P是正整数，基于第一时钟具有第一时钟速率，操作Q执行单元以实现指令的P执行，Q是小于P且大于1的正整数，每个执行单元基于具有第二时钟的第二时钟来操作速率高于第一时钟的第一时钟速率，并且其中第二时钟的第二时钟速率等于第一时钟的第一时钟速率乘以比率P / Q。

2. 发明授权

US5786715A Programmable digital frequency multiplier 失效
标题翻译：可编程数字倍频器
公开(公告)号：US5786715A
公开(公告)日：1998-07-28
申请号：US667430
申请日：1996-06-21
申请人： Sameer D. Halepete
发明人： Sameer D. Halepete
IPC分类号： H03K3/03 , H03K5/13 , H03L7/081 , H03L7/16 , H03B19/00
CPC分类号： H03L7/0812 , H03K3/0315 , H03K5/131 , H03L7/16
摘要： A programmable digital frequency multiplier includes either a delay locked loop with an input clock or a ring oscillator which generates multiple phase delayed clock signals having a common frequency equal to that of the input clock and a corresponding number of equidistant phases. In the delay locked loop, a phase comparator compares the phase of the input clock as received by the first inverter circuit with the phase of the output of the last inverter circuit and generates an error signal which is used as a circuit bias control signal for each of the inverter circuits, thereby controlling the phase delay through each inverter circuit. The multiple inverter circuit output signals are individually gated in separate NOR gates with a corresponding number of frequency programming bits. The resulting NORed output signals are then processed together in an exclusive-NOR gate, thereby generating an output signal having a frequency which is an integer multiple of the input clock frequency with the integer multiple corresponding to the bit pattern of the frequency programming bits.
摘要翻译：可编程数字倍频器包括具有输入时钟的延迟锁定环或环形振荡器，其产生具有等于输入时钟的公共频率的相位延迟时钟信号和相应数量的等距相位。在延迟锁定环路中，相位比较器将第一反相器电路接收的输入时钟的相位与最后的反相器电路的输出的相位进行比较，并产生用作每个电路偏置控制信号的误差信号的逆变器电路，从而控制通过每个逆变器电路的相位延迟。多个逆变器电路输出信号分别在具有相应数量的频率编程位的分离的或非门中选通。所产生的NORed输出信号在异或或非门中一起处理，从而产生具有与频率编程位的位模式对应的整数倍的输入时钟频率的整数倍的频率的输出信号。

3. 发明授权

US5612645A Dynamic MOSFET threshold voltage controller 失效
标题翻译：动态MOSFET阈值电压控制器
公开(公告)号：US5612645A
公开(公告)日：1997-03-18
申请号：US566020
申请日：1995-12-01
申请人： Sameer D. Halepete
发明人： Sameer D. Halepete
IPC分类号： G05F3/20 , G05F1/10
CPC分类号： G05F3/205
摘要： A threshold voltage controller circuit for controlling the threshold voltage of complementary metal oxide semiconductor field effect transistors (CMOSFETs) integrated within an integrated circuit includes a test circuit, a clocked voltage comparator and voltage ramp generator. The test circuit simulates a critical signal path within the integrated circuit by receiving a first clock signal and providing in response thereto a corresponding delayed version of such clock signal. The clocked voltage comparator compares the voltage of the delayed clock signal output from the test circuit with a reference voltage and, in response to a second clock signal which is delayed with respect to the first clock signal, asserts a binary output signal high or low if the clock delay introduced by the test circuit is higher or lower, respectively, than desired. The voltage ramp generator, in response to the binary output signal from the clocked voltage comparator, generates an increasing or decreasing voltage ramp which is applied to the semiconductor substrate and well of the integrated circuit for increasing or decreasing the back bias thereto, thereby increasing or decreasing the threshold voltages of the CMOSFETs, respectively.
摘要翻译：用于控制集成在集成电路内的互补金属氧化物半导体场效应晶体管（CMOSFET）的阈值电压的阈值电压控制器电路包括测试电路，时钟脉冲电压比较器和电压斜坡发生器。测试电路通过接收第一时钟信号并且响应于该时钟信号的相应延迟版本来模拟集成电路内的关键信号路径。时钟电压比较器将从测试电路输出的延迟时钟信号的电压与参考电压进行比较，并且响应于相对于第一时钟信号被延迟的第二时钟信号，将二进制输出信号置为高电平或低电平，如果测试电路引入的时钟延迟分别高于或低于期望值。电压斜坡发生器响应于来自时钟脉冲电压比较器的二进制输出信号产生增加或减小的电压斜坡，其被施加到集成电路的半导体衬底和阱，以增加或减小其偏置，从而增加或减小分别降低CMOSFET的阈值电压。

4. 发明授权

US07085184B1 Delayed bitline leakage compensation circuit for memory devices 有权
标题翻译：用于存储器件的延迟位线泄漏补偿电路
公开(公告)号：US07085184B1
公开(公告)日：2006-08-01
申请号：US10951825
申请日：2004-09-27
申请人： Steven T. Walther , Scott B. Kuusinen , Sameer D. Halepete
发明人： Steven T. Walther , Scott B. Kuusinen , Sameer D. Halepete
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/12
摘要： A delayed bitline leakage compensation circuit for memory devices is disclosed. The delayed bitline leakage compensation circuit includes a bitline leakage model circuit for modeling discharge of a bitline by leakage current in a read operation. It further has a delayed charge signal generator for generating a delayed charge signal in response to the bitline leakage model circuit discharging to approximately a discharge threshold. The delayed charge signal generator is deactivated if the bitline is discharged by a selected memory cell. Moreover, the delayed bitline leakage compensation circuit includes a delayed charge circuit for charging the bitline in response to the delayed charge signal.
摘要翻译：公开了一种用于存储器件的延迟位线泄漏补偿电路。延迟位线泄漏补偿电路包括位线泄漏模型电路，用于在读取操作中通过泄漏电流对位线的放电进行建模。它还具有延迟的充电信号发生器，用于响应于位线泄漏模型电路放电到大致的放电阈值来产生延迟的充电信号。如果位线由所选择的存储单元放电，则延迟的充电信号发生器被去激活。此外，延迟位线泄漏补偿电路包括延迟的充电电路，用于响应延迟的充电信号对位线充电。

5. 发明授权

US5640115A Self-enabling latch 失效
标题翻译：自启动闩锁
公开(公告)号：US5640115A
公开(公告)日：1997-06-17
申请号：US566049
申请日：1995-12-01
申请人： Sameer D. Halepete , James Burr
发明人： Sameer D. Halepete , James Burr
IPC分类号： H03K3/037 , H03K3/356
CPC分类号： H03K3/35606 , H03K3/037
摘要： A self-enabling latch includes a pair of pass transistors, a pair of cross-coupled inverters, an EXCLUSIVE-NOR logic gate and a differential amplifier. The pass transistors receive a differential input data signal which is selectively latched by the cross-coupled inverters. The EXCLUSIVE-NOR logic gate also receives the input data signal and compares it with the latched data signal to provide a control signal for the amplifier. The control signal is active when the present input data is different from the previously latched data. The amplifier, enabled by the active control signal, amplifies a differential clock signal to provide an enabling signal for the pass transistors which thereby present the new input data to the cross-coupled inverters for latching.
摘要翻译：自启动锁存器包括一对传输晶体管，一对交叉耦合的反相器，一个EXCLUSIVE-NOR逻辑门和一个差分放大器。传输晶体管接收由交叉耦合的反相器选择性锁存的差分输入数据信号。 EXCLUSIVE-NOR逻辑门还接收输入数据信号并将其与锁存数据信号进行比较，以提供放大器的控制信号。当当前输入数据与先前锁存的数据不同时，控制信号有效。由有源控制信号使能的放大器放大差分时钟信号，为通过晶体管提供使能信号，从而将新的输入数据呈现给交叉耦合的反相器进行锁存。

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