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1. 发明授权

US4409655A Hierarchial memory ring protection system using comparisons of requested and previously accessed addresses 失效
标题翻译：层次结构内存环保护系统，使用比较请求和以前访问过的地址
公开(公告)号：US4409655A
公开(公告)日：1983-10-11
申请号：US143981
申请日：1980-04-25
申请人： Steven Wallach , Kenneth D. Holberger , David L. Keating , Steven M. Staudaher
发明人： Steven Wallach , Kenneth D. Holberger , David L. Keating , Steven M. Staudaher
IPC分类号： G06F9/26 , G06F9/30 , G06F11/10 , G06F12/08 , G06F12/10 , G06F12/14 , G06F9/00 , G06F9/32 , G06F9/34
CPC分类号： G06F9/26 , G06F11/10 , G06F12/0802 , G06F12/0857 , G06F12/1009 , G06F12/14 , G06F9/30 , G06F11/106
摘要： A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses. The system uses hierarchical memory storage using in a particular embodiment eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The segment locations are designated by successive segment numbers having a descending order of protection with reference to data accesses thereto. A current address for data access includes a segment identification and a comparison is made with the segment identification of a preceding address to determine whether access can be made by the current address.
摘要翻译：数据处理系统处理可从十六位逻辑地址或三十二位逻辑地址导出的二十二位逻辑地址。该系统在特定实施例中使用分层存储器存储使用八个存储段（环），根据不同的权限级别以特权方式对环进行访问。段位置由具有参考其数据访问的保护降序的连续段号指定。用于数据访问的当前地址包括段标识，并且与先前地址的段标识进行比较，以确定是否可以由当前地址进行访问。

2. 发明授权

US4532590A Data processing system having a unique address translation unit 失效
标题翻译：数据处理系统具有唯一的地址转换单元
公开(公告)号：US4532590A
公开(公告)日：1985-07-30
申请号：US451899
申请日：1982-12-21
申请人： Steven Wallach , Kenneth D. Holberger , Steven M. Staudaner , Carl Henry
发明人： Steven Wallach , Kenneth D. Holberger , Steven M. Staudaner , Carl Henry
IPC分类号： G06F9/26 , G06F9/318 , G06F11/10 , G06F11/14 , G06F12/02 , G06F12/06 , G06F12/08 , G06F12/10 , G06F12/14 , G06F9/32
CPC分类号： G06F9/3017 , G06F11/10 , G06F11/14 , G06F12/0292 , G06F12/0802 , G06F12/1009 , G06F12/14 , G06F9/26 , G06F11/106 , G06F12/0623
摘要： A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.
摘要翻译：一种数据处理系统，其处理可从十六位逻辑地址或三十二位逻辑地址导出的二十二位逻辑地址，后者通过唯一的转换装置转换成物理地址。该系统包括用于解码基本指令集和扩展指令集的宏指令的装置，每个宏指令本身都包含唯一地标识要被解码的指令类型的所选位模式。解码的宏指令提供一个或多个微指令的起始地址，该地址被提供给唯一的微指令排序单元，其适当地解码每个微指令的选定字段以获得每个连续的微指令。该系统使用八个存储段（环）的分层存储器存储，根据不同级别的权限访问以特权方式控制的环。存储器系统使用一组主存储器模块，其通过双端口高速缓冲存储器与中央处理器系统连接，在主存储器和高速缓冲存储器之间块数据传输由存储体控制器单元控制。

3. 发明授权

US4386399A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US4386399A
公开(公告)日：1983-05-31
申请号：US143561
申请日：1980-04-25
申请人： Edward Rasala , Steven Wallach , Carl J. Alsing , Kenneth D. Holberger , Charles J. Holland , Thomas West , James M. Guyer , Richard W. Coyle , Michael L. Ziegler , Michael B. Druke
发明人： Edward Rasala , Steven Wallach , Carl J. Alsing , Kenneth D. Holberger , Charles J. Holland , Thomas West , James M. Guyer , Richard W. Coyle , Michael L. Ziegler , Michael B. Druke
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30 , G06F9/34 , G06F11/10 , G06F11/14 , G06F12/08 , G06F12/10 , G06F12/14 , G06F13/00 , G06F9/36
CPC分类号： G06F12/0857 , G06F11/10 , G06F11/14 , G06F12/0802 , G06F12/1009 , G06F12/14 , G06F9/26 , G06F9/3013 , G06F9/30185 , G06F9/30196 , G06F9/342 , G06F11/106
摘要： A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.
摘要翻译：一种数据处理系统，其处理可从十六位逻辑地址或三十二位逻辑地址导出的二十二位逻辑地址，后者通过唯一的转换装置转换成物理地址。该系统包括用于解码基本指令集和扩展指令集的宏指令的装置，每个宏指令本身都包含唯一地标识要被解码的指令类型的所选位模式。解码的宏指令提供一个或多个微指令的起始地址，该地址被提供给唯一的微指令排序单元，其适当地解码每个微指令的选定字段以获得每个连续的微指令。该系统使用八个存储段（环）的分层存储器存储，根据不同级别的权限访问以特权方式控制的环。存储器系统使用一组主存储器模块，其通过双端口高速缓冲存储器与中央处理器系统连接，在主存储器和高速缓冲存储器之间块数据传输由存储体控制器单元控制。

4. 发明授权

US4434459A Data processing system having instruction responsive apparatus for both a basic and an extended instruction set 失效
标题翻译：具有用于基本和扩展指令集的指令响应装置的数据处理系统
公开(公告)号：US4434459A
公开(公告)日：1984-02-28
申请号：US143982
申请日：1980-04-25
申请人： Charles J. Holland , Steven Wallach , Carl J. Alsing
发明人： Charles J. Holland , Steven Wallach , Carl J. Alsing
IPC分类号： G06F9/26 , G06F9/318 , G06F9/38 , G06F9/48 , G06F11/10 , G06F12/14 , G06F9/00
CPC分类号： G06F9/4812 , G06F11/10 , G06F12/1491 , G06F9/268 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/3822 , G06F11/106
摘要： A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The instruction responsive apparatus thereof responds to unique microinstructions which, for example, provide for the selection of one of a plurality of interrupt routines each corresponding to an interrupt request from a different external device, provide for the sequential loading of a plurality of segment identification registers each pointing to selected memory management tables associated with a segment storage region of main memory, provide for a program counter relative jump operation, provide for zero-extending or sign-extending 16-bit words to 32-bit words having the same value, and provide for the multiplication of the lower 16 bits of two 32-bit accumulators and the sign-extension of the 16-bit result to form a 32-bit word.
摘要翻译：一种数据处理系统，其处理可从十六位逻辑地址或三十二位逻辑地址导出的二十二位逻辑地址，后者通过唯一的转换装置转换成物理地址。该系统包括用于解码基本指令集和扩展指令集的宏指令的装置，每个宏指令本身都包含唯一地标识要被解码的指令类型的所选位模式。其指令响应装置响应于唯一的微指令，其例如提供对来自不同外部设备的中断请求的多个中断程序中的一个的选择，提供多个段识别寄存器的顺序加载每个指向与主存储器的段存储区域相关联的选择的存储器管理表，提供程序计数器相对跳转操作，向具有相同值的32位字提供零扩展或符号扩展16位字，以及提供两个32位累加器的低16位的乘法和16位结果的符号扩展以形成32位字。

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