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1. 发明授权

US07531079B1 Method and apparatus for uniform electropolishing of damascene IC structures by selective agitation 失效
标题翻译：通过选择性搅拌均匀电解抛光镶嵌IC结构的方法和装置
公开(公告)号：US07531079B1
公开(公告)日：2009-05-12
申请号：US11065708
申请日：2005-02-23
申请人： Steven T. Mayer , John S. Drewery
发明人： Steven T. Mayer , John S. Drewery
IPC分类号： C25F3/16
CPC分类号： B23H5/08 , C25F3/16 , H01L21/32125 , H01L21/7684
摘要： The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process. Thus, methods of the invention are electropolishing methods, which in some cases include mechanical polishing elements.
摘要翻译：本发明涉及在大范围的特征尺寸上具有凹陷和凸起特征的金属表面的平坦化的装置和方法。本发明通过增加相对于凹陷区域的凸起区域中的流体搅拌来实现。也就是说，作为金属膜轮廓上的仰角的函数来搅动或更换电抛光浴液的搅动。海拔越高，浴液的运动或汇率越高。在本发明的优选方法中，通过使用在电解抛光过程中在晶片表面上移动（接近或接触）的微孔电解抛光垫来实现该搅拌。因此，本发明的方法是电抛光方法，其在一些情况下包括机械抛光元件。

2. 发明授权

US06709565B2 Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation 有权
标题翻译：通过选择性搅拌均匀电解抛光镶嵌结构的方法和装置
公开(公告)号：US06709565B2
公开(公告)日：2004-03-23
申请号：US09967075
申请日：2001-09-28
申请人： Steven T. Mayer , Robert J. Contolini , Eliot K. Broadbent , John S. Drewery
发明人： Steven T. Mayer , Robert J. Contolini , Eliot K. Broadbent , John S. Drewery
IPC分类号： B23H1100
CPC分类号： B23H5/08 , H01L21/32115 , H01L21/3212 , H01L21/32134
摘要： The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process. Thus, methods of the invention are electropolishing methods, which in some cases include mechanical polishing elements.
摘要翻译：本发明涉及在大范围的特征尺寸上具有凹陷和凸起特征的金属表面的平坦化的装置和方法。本发明通过增加相对于凹陷区域的凸起区域中的流体搅拌来实现。也就是说，作为金属膜轮廓上的仰角的函数来搅动或更换电抛光浴液的搅动。海拔越高，浴液的运动或汇率越高。在本发明的优选方法中，通过使用在电解抛光过程中在晶片表面上移动（接近或接触）的微孔电解抛光垫来实现该搅拌。因此，本发明的方法是电抛光方法，其在一些情况下包括机械抛光元件。

3. 发明授权

US08795482B1 Selective electrochemical accelerator removal 有权
标题翻译：选择性电化学促进剂去除
公开(公告)号：US08795482B1
公开(公告)日：2014-08-05
申请号：US13572483
申请日：2012-08-10
申请人： Steven T. Mayer , Marshall R. Stowell , John S. Drewery , Richard S. Hill , Timothy M. Archer , Avishai Kepten
发明人： Steven T. Mayer , Marshall R. Stowell , John S. Drewery , Richard S. Hill , Timothy M. Archer , Avishai Kepten
IPC分类号： C25D5/02 , C25F3/16
CPC分类号： B23H5/08 , C25F3/16 , H01L21/02068 , H01L21/2885 , H01L21/32115 , H01L21/7684
摘要： Methods and apparatus are provided for planar metal plating on a workpiece having a surface with recessed regions and exposed surface regions; comprising the steps of: causing a plating accelerator to become attached to said surface including the recessed and exposed surface regions; selectively removing the plating accelerator from the exposed surface regions without performing substantial metal plating on the surface; and after removal of plating accelerator is at least partially complete, plating metal onto the surface, whereby the plating accelerator remaining attached to the surface increases the rate of metal plating in the recessed regions relative to the rate of metal plating in the exposed surface regions.
摘要翻译：提供了用于在具有凹陷区域和暴露表面区域的表面的工件上进行平面金属电镀的方法和装置; 包括以下步骤：使电镀加速器附着到包括凹入和暴露的表面区域的所述表面; 选择性地从暴露的表面区域去除电镀加速器，而不在表面上进行实质的金属电镀; 在去除电镀促进剂至少部分完成后，将金属镀在表面上，由此保持附着在表面上的电镀加速剂相对于露出的表面区域中的金属电镀速率增加凹陷区域中的金属电镀速率。

4. 发明授权

US08268154B1 Selective electrochemical accelerator removal 有权
标题翻译：选择性电化学促进剂去除
公开(公告)号：US08268154B1
公开(公告)日：2012-09-18
申请号：US12860787
申请日：2010-08-20
申请人： Steven T. Mayer , John S. Drewery , Richard S. Hill , Timothy M. Archer , Avishai Kepten
发明人： Steven T. Mayer , John S. Drewery , Richard S. Hill , Timothy M. Archer , Avishai Kepten
IPC分类号： C25D5/02
CPC分类号： B23H5/08 , C25F3/16 , H01L21/02068 , H01L21/2885 , H01L21/32115 , H01L21/7684
摘要： Methods and apparatus are provided for planar metal plating on a workpiece having a surface with recessed regions and exposed surface regions; comprising the steps of: causing a plating accelerator to become attached to said surface including the recessed and exposed surface regions; selectively removing the plating accelerator from the exposed surface regions without performing substantial metal plating on the surface; and after removal of plating accelerator is at least partially complete, plating metal onto the surface, whereby the plating accelerator remaining attached to the surface increases the rate of metal plating in the recessed regions relative to the rate of metal plating in the exposed surface regions.
摘要翻译：提供了用于在具有凹陷区域和暴露表面区域的表面的工件上进行平面金属电镀的方法和装置; 包括以下步骤：使电镀加速器附着到包括凹入和暴露的表面区域的所述表面; 选择性地从暴露的表面区域去除电镀加速器，而不在表面上进行实质的金属电镀; 在去除电镀促进剂至少部分完成后，将金属镀在表面上，由此保持附着在表面上的电镀加速剂相对于露出的表面区域中的金属电镀速率增加凹陷区域中的金属电镀速率。

5. 发明授权

US07682498B1 Rotationally asymmetric variable electrode correction 有权
标题翻译：旋转不对称可变电极校正
公开(公告)号：US07682498B1
公开(公告)日：2010-03-23
申请号：US11179984
申请日：2005-07-11
申请人： Steven T. Mayer , John S. Drewery
发明人： Steven T. Mayer , John S. Drewery
IPC分类号： B23H3/00 , C25D5/00 , C25D5/18 , C25D17/10 , B23H7/14 , C25D21/12
CPC分类号： B23H3/04 , C25D5/04 , C25D5/18 , C25D7/123 , C25D17/001 , C25D17/12 , C25D21/12
摘要： A work piece is electroplated or electroplanarized using an azimuthally asymmetric electrode. The azimuthally asymmetric electrode is rotated with respect to the work piece (i.e., either or both of the work piece and the electrode may be rotating). The azimuthal asymmetry provides a time-of-exposure correction to the current distribution reaching the work piece. In some embodiments, the total current is distributed among a plurality of electrodes in a reaction cell in order to tailor the current distribution in the electrolyte over time. Focusing elements may be used to create “virtual electrode” in proximity to the surface of the work piece to further control the current distribution in the electrolyte during plating or planarization.
摘要翻译：使用方位不对称电极对工件进行电镀或电平面化处理。方位不对称电极相对于工件旋转（即，工件和电极中的任一个或两者可以旋转）。方位不对称性提供了到达工件的当前分布的曝光时间校正。在一些实施例中，总电流分布在反应池中的多个电极之间，以便随着时间的推移来调整电解质中的电流分布。可以使用聚焦元件在工件的表面附近产生“虚拟电极”，以进一步控制在电镀或平坦化期间电解液中的电流分布。

6. 发明授权

US07449098B1 Method for planar electroplating 失效
标题翻译：平面电镀方法
公开(公告)号：US07449098B1
公开(公告)日：2008-11-11
申请号：US10739822
申请日：2003-12-17
申请人： Steven T. Mayer , Jonathan D. Reid , Mark L. Rea , Ismail T. Emesh , Henner W. Meinhold , John S. Drewery
发明人： Steven T. Mayer , Jonathan D. Reid , Mark L. Rea , Ismail T. Emesh , Henner W. Meinhold , John S. Drewery
IPC分类号： C25D5/02 , C25D5/34 , C25D5/48 , C25D7/12
CPC分类号： B23H5/08 , C25D5/06 , C25D5/22 , C25D5/34 , C25D5/48 , C25D7/123 , C25F3/16 , H01L21/2885 , H01L21/3212 , H01L21/7684 , H01L21/76877
摘要： A disclosed form of mechanically assisted electroplating leads to a flat, thin, overburden. In one example, an accelerator is deposited on a copper surface and mechanically removed in a simplified CMP-like apparatus. The wafer is then plated in an electrolyte containing little or no accelerating additives.
摘要翻译：一种公开的机械辅助电镀形式导致平坦，薄的覆盖层。在一个实例中，加速器沉积在铜表面上并在简化的类似CMP的装置中机械地去除。然后将晶片镀在含有很少或没有加速添加剂的电解质中。

7. 发明授权

US6080287A Method and apparatus for ionized physical vapor deposition 失效
标题翻译：电离物理气相沉积的方法和装置
公开(公告)号：US6080287A
公开(公告)日：2000-06-27
申请号：US73141
申请日：1998-05-06
申请人： John S. Drewery , Thomas J. Licata
发明人： John S. Drewery , Thomas J. Licata
IPC分类号： C23C14/32 , C23C14/34 , C23C14/35 , H01J37/32 , H01J37/34 , H01L21/203 , H01L21/285
CPC分类号： C23C14/345 , C23C14/35 , C23C14/358 , H01J37/321 , H01J37/32477 , H01J37/3408 , H01J37/3429
摘要： Ionized physical vapor deposition (IPVD) is provided by a method of apparatus for sputtering conductive metal coating material from an annular magnetron sputtering target. The sputtered material is ionized in a processing space between the target and a substrate by generating a dense plasma in the space with energy coupled from a coil located outside of the vacuum chamber behind a dielectric window in the chamber wall at the center of the opening in the sputtering target. Faraday type shields physically shield the window to prevent coating material from coating the window, while allowing the inductive coupling of energy from the coil into the processing space. The location of the coil in the plane of the target or behind the target allows the target to wafer spacing to be chosen to optimize film deposition rate and uniformity, and also provides for the advantages of a ring-shaped source without the problems associated with unwanted deposition in the opening at the target center.
摘要翻译：电离物理气相沉积（IPVD）是通过一种用于从环形磁控溅射靶溅射导电金属涂层材料的设备的方法提供的。溅射的材料在目标和基板之间的处理空间中被离子化，通过在空间中产生致密的等离子体，其能量从位于真空室外面的线圈耦合到位于开口中心的室壁中的电介质窗口之后溅射靶。法拉第型屏蔽物理屏蔽窗户，防止涂料涂覆窗户，同时允许将线圈的能量感应耦合到处理空间。线圈在目标平面中或靶子后面的位置允许选择目标晶片间距以优化膜沉积速率和均匀性，并且还提供环形源的优点，而没有与不期望的相关联的问题沉积在目标中心的开口处。

8. 发明授权

US06756307B1 Apparatus for electrically planarizing semiconductor wafers 有权
标题翻译：用于使半导体晶片电平面化的装置
公开(公告)号：US06756307B1
公开(公告)日：2004-06-29
申请号：US10209171
申请日：2002-07-29
申请人： John Kelly , Wilbert G. H. van den Hoek , John S. Drewery
发明人： John Kelly , Wilbert G. H. van den Hoek , John S. Drewery
IPC分类号： H01L21302
CPC分类号： H01L21/32115 , B23H5/08 , C25F3/16 , H01L21/32134 , H01L21/7684
摘要： The present invention pertains to apparatus and methods for electroplanarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by use of a flexible planar cathode and a spacing pad thereon. Methods of the invention are electropolishing methods. During electroplanarization, the flexible planar cathode conforms to the global contour of the work piece (e.g. a wafer) while the spacing pad conforms to local topography of the metal layer being planarized. In this way, dishing is reduced in the final planarized metal layer.
摘要翻译：本发明涉及在特征尺寸较大的范围内具有凹凸特征和凸起特征的金属表面的电解平面化的装置和方法。本发明通过使用柔性平面阴极和其上的间隔垫来实现。本发明的方法是电抛光方法。在电平面化期间，柔性平面阴极符合工件（例如晶片）的全局轮廓，而间隔垫符合被平坦化的金属层的局部形貌。以这种方式，最终的平坦化金属层中的凹陷减少。

9. 发明授权

US06790773B1 Process for forming barrier/seed structures for integrated circuits 有权
标题翻译：用于形成用于集成电路的屏障/种子结构的工艺
公开(公告)号：US06790773B1
公开(公告)日：2004-09-14
申请号：US10232445
申请日：2002-08-28
申请人： John S. Drewery , Ronald A. Powell
发明人： John S. Drewery , Ronald A. Powell
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L2221/1089
摘要： A process and structure are provided that allows electroplating to fill sub-micron, high aspect ratio features using a non-conformal conductive layer between the dielectric layer and the platability layer. The conductive layer is a relatively thick layer overlying the planar surface of the wafer and the bottom of the features to be filled. Little or no material of the conductive layer is formed on the feature sidewalls. The thick conductive layer on the field provides adequate conductivity for uniform electroplating, while the absence of significant conductive material on the sidewalls decreases the aspect ratio of the feature and makes void-free filling easier to accomplish with electroplating. Further, the absence of significant material on the sidewalls allows a thicker barrier layer to be formed for higher reliability.
摘要翻译：提供了一种工艺和结构，其允许电镀使用介电层和可镀层之间的非保形导电层来填充亚微米高的纵横比特征。导电层是覆盖晶片的平面表面和要填充的特征的底部的相对较厚的层。在特征侧壁上形成很少或者没有导电层的材料。场上的厚导电层为均匀电镀提供了足够的导电性，同时侧壁上不存在显着的导电材料会降低特征的纵横比，并使电镀更容易实现无空隙填充。此外，在侧壁上不存在显着的材料允许形成更厚的阻挡层以获得更高的可靠性。

10. 发明授权

US06774039B1 Process scheme for improving electroplating performance in integrated circuit manufacture 有权
标题翻译：用于提高集成电路制造中电镀性能的工艺方案
公开(公告)号：US06774039B1
公开(公告)日：2004-08-10
申请号：US10215156
申请日：2002-08-08
申请人： John S. Drewery
发明人： John S. Drewery
IPC分类号： H01L2144
CPC分类号： H01L21/2885 , H01L21/76877
摘要： Copper bus bars are formed between adjacent die on a wafer during the process flow. The bus bars are between 50 and 100 &mgr;m wide and between 2 and 5 &mgr;m deep. A barrier layer is formed between the bus bars and the die to prevent copper diffusion. A dielectric layer is deposited over the bus bars and die and etched with contacts and features, such as vias. A seed layer is subsequently deposited over the wafer, which allows electrical conductance between the bus bars and the die during a subsequent electroplating process to fill the features and contacts. The bus bars carry electroplating current from the die edge to the die center. As a result, current does not need to be carried by a low sheet resistivity seed layer from the wafer edge to the center. This allows the seed layer to be thinner and of materials other than copper. Further, thinner seed layers allow thicker barrier layer for more reliability.
摘要翻译：在处理流程期间，在晶片上的相邻裸片之间形成铜母线。母线宽度在50到100毫米之间，深度在2到5毫米之间。在汇流条和模具之间形成阻挡层以防止铜扩散。电介质层沉积在汇流条上并冲模并用触点和特征（例如通孔）进行蚀刻。晶种层随后沉积在晶片上，这允许在随后的电镀过程期间母线和裸片之间的电导率以填充特征和接触。汇流条将电镀电流从模具边缘运送到模具中心。结果，电流不需要由薄片电阻率籽晶层从晶片边缘到中心承载。这允许种子层更薄并且除了铜以外的材料。此外，更薄的种子层允许更厚的阻挡层更可靠。

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