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1. 发明申请

US20090240753A1 METHOD, HARDWARE PRODUCT, AND COMPUTER PROGRAM PRODUCT FOR USING A DECIMAL FLOATING POINT UNIT TO EXECUTE FIXED POINT INSTRUCTIONS 有权
标题翻译：方法，硬件产品和计算机程序产品，用于使用十进制浮点单元执行固定点说明
公开(公告)号：US20090240753A1
公开(公告)日：2009-09-24
申请号：US12051333
申请日：2008-03-19
申请人： Steven R. Carlough , Adam B. Collura , Mark A. Erle , Wen H. Li , Eric M. Schwarz
发明人： Steven R. Carlough , Adam B. Collura , Mark A. Erle , Wen H. Li , Eric M. Schwarz
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F2207/4911
摘要： A decimal floating point (DFP) unit is used to execute fixed point instructions. Two or more operands are accepted, wherein each operand is in a packed binary coded decimal (BCD) format. Any invalid BCD formats are detected by checking the operands for any invalid BCD codes. It is determined if an exception flag exists and, if so, outputting the flag; it is determined if a condition code exists and, if so, outputting the code. An operation is performed on the two or more operands to generate a result; wherein the operation takes place directly on BCD data, thus using the DFP unit to perform a BCD operation; appending a result sign to the result of the operation; and providing the result of the operation and the appended result sign as a result output in a packed BCD format.
摘要翻译：使用十进制浮点（DFP）单位执行固定点指令。接受两个或多个操作数，其中每个操作数都是压缩的二进制编码十进制（BCD）格式。通过检查任何无效的BCD代码的操作数来检测任何无效的BCD格式。确定是否存在异常标志，如果是，则输出该标志; 确定条件代码是否存在，如果是，则输出代码。对两个或更多个操作数执行操作以产生结果; 其中操作直接发生在BCD数据上，因此使用DFP单元执行BCD操作; 将结果符号附加到操作结果; 并提供操作结果和附加结果符号作为输出的压缩BCD格式的结果。

2. 发明授权

US08572141B2 Execution of fixed point instructions using a decimal floating point unit 有权
标题翻译：使用十进制浮点单元执行定点指令
公开(公告)号：US08572141B2
公开(公告)日：2013-10-29
申请号：US12051333
申请日：2008-03-19
申请人： Steven R. Carlough , Adam B. Collura , Mark A. Erle , Wen H. Li , Eric M. Schwarz
发明人： Steven R. Carlough , Adam B. Collura , Mark A. Erle , Wen H. Li , Eric M. Schwarz
IPC分类号： G06F15/00 , G06F7/00 , G06F7/52
CPC分类号： G06F7/483 , G06F2207/4911
摘要： A decimal floating point (DFP) unit is used to execute fixed point instructions. Two or more operands are accepted, wherein each operand is in a packed binary coded decimal (BCD) format. Any invalid BCD formats are detected by checking the operands for any invalid BCD codes. It is determined if an exception flag exists and, if so, outputting the flag; it is determined if a condition code exists and, if so, outputting the code. An operation is performed on the two or more operands to generate a result; wherein the operation takes place directly on BCD data, thus using the DFP unit to perform a BCD operation; appending a result sign to the result of the operation; and providing the result of the operation and the appended result sign as a result output in a packed BCD format.
摘要翻译：使用十进制浮点（DFP）单位执行固定点指令。接受两个或多个操作数，其中每个操作数都是压缩的二进制编码十进制（BCD）格式。通过检查任何无效的BCD代码的操作数来检测任何无效的BCD格式。确定是否存在异常标志，如果是，则输出该标志; 确定条件代码是否存在，如果是，则输出代码。对两个或更多个操作数执行操作以产生结果; 其中操作直接发生在BCD数据上，因此使用DFP单元执行BCD操作; 将结果符号附加到操作结果; 并提供操作结果和附加结果符号作为输出的压缩BCD格式的结果。

3. 发明申请

US20090210659A1 PROCESSOR AND METHOD FOR WORKAROUND TRIGGER ACTIVATED EXCEPTIONS 失效
标题翻译：用于替代触发器激活的例外的处理器和方法
公开(公告)号：US20090210659A1
公开(公告)日：2009-08-20
申请号：US12032105
申请日：2008-02-15
申请人： Steven R. Carlough , Adam B. Collura , Wen H. Li , Eric M. Schwarz , Chung-Lung Kevin Shum
发明人： Steven R. Carlough , Adam B. Collura , Wen H. Li , Eric M. Schwarz , Chung-Lung Kevin Shum
IPC分类号： G06F9/30 , G06F9/44
CPC分类号： G06F9/3861 , G06F9/3017 , G06F9/322 , G06F9/328 , G06F11/0721 , G06F11/0793
摘要： A processor includes a microarchitecture for working around a processing flaw, the microarchitecture including: at least one detector adapted for detecting a predetermined state associated with the processing flaw; and at least one mechanism to modify default processor processing behavior; and upon modification of processing behavior, the processing of an instruction involving the processing flaw can be completed by avoiding the processing flaw.
摘要翻译：处理器包括用于处理加工缺陷的微架构，所述微体系结构包括：至少一个检测器，适于检测与所述处理缺陷相关联的预定状态; 以及至少一种修改默认处理器处理行为的机制; 并且在修改处理行为时，可以通过避免处理缺陷来完成涉及处理缺陷的指令的处理。

4. 发明授权

US08443227B2 Processor and method for workaround trigger activated exceptions 失效
标题翻译：解决方法的处理器和方法触发激活的异常
公开(公告)号：US08443227B2
公开(公告)日：2013-05-14
申请号：US12032105
申请日：2008-02-15
申请人： Steven R. Carlough , Adam B. Collura , Wen H. Li , Eric M. Schwarz , Chung-Lung Kevin Shum
发明人： Steven R. Carlough , Adam B. Collura , Wen H. Li , Eric M. Schwarz , Chung-Lung Kevin Shum
IPC分类号： G06F11/00
CPC分类号： G06F9/3861 , G06F9/3017 , G06F9/322 , G06F9/328 , G06F11/0721 , G06F11/0793
摘要： A processor includes a microarchitecture for working around a processing flaw, the microarchitecture including: at least one detector adapted for detecting a predetermined state associated with the processing flaw; and at least one mechanism to modify default processor processing behavior; and upon modification of processing behavior, the processing of an instruction involving the processing flaw can be completed by avoiding the processing flaw.
摘要翻译：处理器包括用于处理加工缺陷的微架构，所述微体系结构包括：至少一个检测器，适于检测与所述处理缺陷相关联的预定状态; 以及至少一种修改默认处理器处理行为的机制; 并且在修改处理行为时，可以通过避免处理缺陷来完成涉及处理缺陷的指令的处理。

5. 发明授权

US08161091B2 Method for performing decimal floating point addition 有权
标题翻译：执行十进制浮点加法的方法
公开(公告)号：US08161091B2
公开(公告)日：2012-04-17
申请号：US12358911
申请日：2009-01-23
申请人： Steven R. Carlough , Wen H. Li , Eric M. Schwarz
发明人： Steven R. Carlough , Wen H. Li , Eric M. Schwarz
IPC分类号： G06F7/485
CPC分类号： G06F7/4912 , G06F2207/4911
摘要： A method for performing a decimal floating point operation including receiving a first operand having a first coefficient and a first exponent into a first register. A second operand having a second coefficient and a second exponent are received into a second register. An operation, either addition or subtraction, associated with the first operand and the second operand is received. Three concurrent calculations are performed on the first operand and the second operand. The three concurrent calculations include: applying the operation to the first operand and the second operand based on a first assumption; applying the operation to the first operand and the second operand based on a second assumption; and applying the operation to the first operand and the second operand based on a third assumption. A final result is selected from the first result, the second result and the third result.
摘要翻译：一种用于执行十进制浮点运算的方法，包括将具有第一系数和第一指数的第一操作数接收到第一寄存器中。具有第二系数和第二指数的第二操作数被接收到第二寄存器中。接收与第一操作数和第二操作数相关联的加法或减法操作。在第一个操作数和第二个操作数上执行三个并发计算。三个并发计算包括：基于第一假设将操作应用于第一操作数和第二操作数; 基于第二假设将操作应用于第一操作数和第二操作数; 以及基于第三假设将所述操作应用于所述第一操作数和所述第二操作数。从第一个结果，第二个结果和第三个结果中选择最终结果。

6. 发明申请

US20090132628A1 Method for Performing Decimal Division 有权
标题翻译：执行十进制分割的方法
公开(公告)号：US20090132628A1
公开(公告)日：2009-05-21
申请号：US12358885
申请日：2009-01-23
申请人： Steven R. Carlough , Paulomi Kadakia , Wen H. Li , Eric M. Schwarz
发明人： Steven R. Carlough , Paulomi Kadakia , Wen H. Li , Eric M. Schwarz
IPC分类号： G06F7/52
CPC分类号： G06F7/4917 , G06F2207/5352
摘要： A method for performing decimal division including receiving a scaled divisor and a scaled dividend into input registers. A subset of multiples of the scaled divisor is stored in a plurality of multiples registers. Quotient digits are calculated in response to the scaled divisor and the scaled dividend. Each quotient digit is calculated in three clock cycles by a pipeline mechanism. The calculating includes selecting a new quotient digit, and calculating a new remainder. Input to the calculating a new remainder includes data from one or more of the multiples registers.
摘要翻译：一种用于执行小数除法的方法，包括将输入寄存器中的缩放除数和缩放的除数接收。缩放除数的倍数的子集存储在多个多个寄存器中。商数是根据缩放除数和缩放除数计算的。每个商数由流水线机构在三个时钟周期内计算。计算包括选择新的商数，并计算新的余数。计算新余数的输入包括来自一个或多个多个寄存器的数据。

7. 发明授权

US07475104B2 System and method for providing a double adder for decimal floating point operations 失效
标题翻译：提供用于十进制浮点运算的双加法器的系统和方法
公开(公告)号：US07475104B2
公开(公告)日：2009-01-06
申请号：US11054687
申请日：2005-02-09
申请人： Steven R. Carlough , Wilhelm E. Haller , Wen H. Li , Eric M. Schwarz
发明人： Steven R. Carlough , Wilhelm E. Haller , Wen H. Li , Eric M. Schwarz
IPC分类号： G06F7/485
CPC分类号： G06F7/4912 , G06F7/483 , G06F7/507
摘要： A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding digits from the first operand and the second operand. Output from each of the adder blocks includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The calculating is performed during a first clock cycle. The system also includes an intermediate result register for storing the sums of the corresponding digits output from each of the plurality of adder blocks, the storing during the first clock cycle. The system further includes a carry chain for storing the carry out indicator output from each of the plurality of adder blocks, the storing occurring during the first clock cycle. The system further includes an incrementer for adding one to each of the sums stored in the intermediate result register, the incrementing occurring during a second clock cycle. In addition, a mechanism is provided for selecting between each of the sums and the sums incremented by one. The input to the mechanism includes the carry chain. The output includes the final sum of the first operand and the second operand. The selecting occurs during the second clock cycle.
摘要翻译：用于执行十进制浮点加法的系统。该系统包括用于输入用于加法运算的第一和第二操作数的输入寄存器。该系统还包括多个加法器块，每个加法器块从第一操作数和第二操作数计算一个或多个相应数字的和。来自每个加法器块的输出包括对应数字的和和相应数字的执行指示符。计算在第一个时钟周期内执行。该系统还包括中间结果寄存器，用于存储从多个加法器块中的每一个输出的相应数字的和，在第一时钟周期期间存储。该系统还包括用于存储来自多个加法器块中的每一个的进位指示符输出的进位链，在第一时钟周期期间发生存储。该系统还包括一个加法器，用于对存储在中间结果寄存器中的每个和加1，在第二时钟周期期间发生递增。此外，提供了一种机制，用于在每个总和和加1之和之间进行选择。机构的输入包括进位链。输出包括第一个操作数和第二个操作数的最后一个和。选择发生在第二个时钟周期。

8. 发明授权

US07519649B2 System and method for performing decimal division 失效
标题翻译：用于执行小数除法的系统和方法
公开(公告)号：US07519649B2
公开(公告)日：2009-04-14
申请号：US11055221
申请日：2005-02-10
申请人： Steven R. Carlough , Paulomi Kadakia , Wen H. Li , Eric M. Schwarz
发明人： Steven R. Carlough , Paulomi Kadakia , Wen H. Li , Eric M. Schwarz
IPC分类号： G06F7/496
CPC分类号： G06F7/4917 , G06F2207/5352
摘要： A method for performing decimal division including receiving a scaled divisor and dividend and storing a subset of the multiples of the scaled divisor. An accumulated quotient is initialized to be equal to zero, a first current remainder is initialized to be equal to the scaled dividend, and a second current remainder is initialized to be equal to the scaled dividend minus the scaled divisor. The following loop is performed until a selected number of quotient digits are produced. An estimated next quotient digit is calculated based on the first digit of the first current remainder. A temp remainder is selected to be either the first current remainder or the second current remainder based on the estimated next quotient digit. A first next remainder is calculated by subtracting one of the stored multiples from the temp remainder, where the stored multiple is selected based on a first digit of the first current remainder. A second next remainder is calculated by subtracting an other one of the stored multiples from the temp remainder, where the other one of the stored multiples is selected based on the first current remainder. An actual quotient digits is calculated based on the estimated next quotient digit, the first current remainder and the first next remainder. The accumulated quotient is updated with the actual next quotient digit. Finally, the first current remainder is set to be equal to the first next remainder and the second current remainder is set to be equal to the second next remainder.
摘要翻译：一种用于执行小数除法的方法，包括接收缩放除数和除数并存储缩放除数的倍数的子集。将累积商初始化为等于零，将第一当前余数初始化为等于缩放后的余数，并将第二电流余数初始化为等于缩放后的除数减去缩放除数。执行以下循环，直到产生所选数量的商数。基于第一当前剩余部分的第一个数字计算估计的下一个商数。基于估计的下一个商数，将临时余量选择为第一当前余数或第二当前余数。通过从临时余数中减去一个存储的倍数来计算第一个下一个余数，其中根据第一个当前余数的第一个数字选择存储的倍数。通过从温度余量中减去另一个存储的倍数来计算第二个剩余部分，其中基于第一当前剩余部分选择存储的倍数中的另一个。基于估计的下一个商数，第一个当前余数和第一个下一个余数来计算实际商数。累积商用实际下一个商数更新。最后，将第一当前余数设置为等于第一下一个余数，并将第二当前余数设置为等于第二个下一个余数。

9. 发明申请

US20090112960A1 System and Method for Providing a Double Adder for Decimal Floating Point Operations 有权
标题翻译：用于提供十进制浮点运算的双加法器的系统和方法
公开(公告)号：US20090112960A1
公开(公告)日：2009-04-30
申请号：US12348579
申请日：2009-01-05
申请人： Steven R. Carlough , Wilhelm E. Haller , Wen H. Li , Eric M. Schwarz
发明人： Steven R. Carlough , Wilhelm E. Haller , Wen H. Li , Eric M. Schwarz
IPC分类号： G06F7/485
CPC分类号： G06F7/4912 , G06F7/483 , G06F7/507
摘要： A method for implementing an adder including receiving a first and second operand. A sum of one or more corresponding digits from the first operand and the second operand is calculated. The calculating is performed by a plurality of adder blocks. Output from the calculating includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The sums of the corresponding digits and the carry out indicators in a carry chain are stored in an intermediate result register. Each of the sums in the intermediate result register is incremented by one. A selection between each of the sums and the sums incremented by one is performed. Input to the selecting includes the carry chain, and the output from the selecting includes a final sum of the first operand and the second operand. The final sum is stored in an output register.
摘要翻译：一种用于实现加法器的方法，包括接收第一和第二操作数。计算来自第一操作数和第二操作数的一个或多个对应数字的和。该计算由多个加法器块执行。来自计算的输出包括相应数字的和和相应数字的进位指示符。进位链中相应数字和进位指示的总和存储在中间结果寄存器中。中间结果寄存器中的每个和增加1。执行每个和之间的选择，并且递增1。选择的输入包括进位链，并且来自选择的输出包括第一操作数和第二操作数的最终和。最后的和存储在输出寄存器中。

10. 发明授权

US07519647B2 System and method for providing a decimal multiply algorithm using a double adder 失效
标题翻译：使用双加法器提供十进制乘法算法的系统和方法
公开(公告)号：US07519647B2
公开(公告)日：2009-04-14
申请号：US11054567
申请日：2005-02-09
申请人： Steven R. Carlough , Wen H. Li , Eric M. Schwarz
发明人： Steven R. Carlough , Wen H. Li , Eric M. Schwarz
IPC分类号： G06F7/496
CPC分类号： G06F7/496 , G06F2207/4911
摘要： A system for performing decimal multiplication including input registers for inputting a multiplier and a multiplicand. The multiplier includes one or more digits. The system also includes one or more two cycle adders and mechanism. The mechanism receives the multiplier and the multiplicand into the input registers. A running sum is reset to zero. The mechanism also performs for each of the digits in the multiplier in order from least significant digit to most significant digit: creating a partial product of the digit and the multiplicand; and adding the partial product to the running sum using the two cycle adders. When the loop is completed for each of the digits in the multiplier, the mechanism outputs the running sum as the result.
摘要翻译：用于执行十进制乘法的系统，包括用于输入乘法器和被乘数的输入寄存器。乘数包括一个或多个数字。该系统还包括一个或多个两个循环加法器和机构。该机制将乘法器和被乘数接收到输入寄存器中。运行总和重置为零。该机制还对乘数中的每个数字执行从最低有效位到最高有效位的顺序：创建数字和被乘数的部分乘积; 并使用两个循环加法器将部分乘积添加到运行总和。当乘法器中的每个数字的循环完成时，机构将输出运行总和作为结果。

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