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1. 发明申请

US20070152216A1 INTERCONNECTION IN AN INSULATING LAYER ON A WAFER 审中-公开
标题翻译：绝缘层上的互连互连
公开(公告)号：US20070152216A1
公开(公告)日：2007-07-05
申请号：US11687663
申请日：2007-03-18
申请人： Steven Lin , Su-Ping Chiu
发明人： Steven Lin , Su-Ping Chiu
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L21/76892
摘要： An interconnection in an insulating layer on a wafer is described herein. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive lines waiting to be repaired. A first conductive layer is filled into the via holes to form two pattern marks. A mask is formed over the wafer to cover the insulating layer and the two pattern marks. The mask located above and between the two pattern marks is removed to form a trench exposing the two pattern marks and a portion of the insulating layer. A second conductive layer is formed over the mask to cover the two exposed pattern marks and the exposed insulating layer. The mask and the second conductive layer above the mask are removed simultaneously.
摘要翻译：本文描述了晶片上的绝缘层中的互连。提供其上具有多条导线的晶片。在导线上形成绝缘层。在绝缘层中形成两个通孔，以露出等待修理的两根导电线。将第一导电层填充到通孔中以形成两个图案标记。在晶片上形成掩模以覆盖绝缘层和两个图案标记。去除位于两个图案标记之上和之间的掩模，以形成暴露两个图案标记和绝缘层的一部分的沟槽。在掩模上形成第二导电层以覆盖两个暴露的图案标记和暴露的绝缘层。掩模和掩模上方的第二导电层同时被去除。

2. 发明授权

US07253093B2 Method for fabricating interconnection in an insulating layer on a wafer 失效
标题翻译：制造晶片绝缘层中互连的方法
公开(公告)号：US07253093B2
公开(公告)日：2007-08-07
申请号：US10906168
申请日：2005-02-05
申请人： Steven G S Lin , Su-Ping Chiu
发明人： Steven G S Lin , Su-Ping Chiu
IPC分类号： H01L21/30
CPC分类号： H01L21/76892
摘要： A method for fabricating an interconnection in an insulating layer on a wafer is described. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive lines waiting to be repaired. A first conductive layer is filled into the via holes to form two pattern marks. A mask is formed over the wafer to cover the insulating layer and the two pattern marks. The mask located above and between the two pattern marks is removed to form a trench exposing the two pattern marks and a portion of the insulating layer. A second conductive layer is formed over the mask to cover the two exposed pattern marks and the exposed insulating layer. The mask and the second conductive layer above the mask are removed simultaneously.
摘要翻译：描述了在晶片上的绝缘层中制造互连的方法。提供其上具有多条导线的晶片。在导线上形成绝缘层。在绝缘层中形成两个通孔，以露出等待修理的两根导电线。将第一导电层填充到通孔中以形成两个图案标记。在晶片上形成掩模以覆盖绝缘层和两个图案标记。去除位于两个图案标记之上和之间的掩模，以形成暴露两个图案标记和绝缘层的一部分的沟槽。在掩模上形成第二导电层以覆盖两个暴露的图案标记和暴露的绝缘层。掩模和掩模上方的第二导电层同时被去除。

3. 发明申请

US20060178001A1 METHOD FOR FABRICATING INTERCONNECTION IN AN INSULATING LAYER ON A WAFER AND STRUCTURE THEREOF 失效
标题翻译：用于在绝缘层上形成互连的方法及其结构
公开(公告)号：US20060178001A1
公开(公告)日：2006-08-10
申请号：US10906168
申请日：2005-02-05
申请人： Steven GS Lin , Su-Ping Chiu
发明人： Steven GS Lin , Su-Ping Chiu
IPC分类号： H01L21/30
CPC分类号： H01L21/76892
摘要： A method for fabricating an interconnection in an insulating layer on a wafer is described. A wafer having a plurality of conductive lines thereon is provided. An insulating layer is formed over the conductive lines. Two via holes are formed in the insulating layer to expose two of the conductive lines waiting to be repaired. A first conductive layer is filled into the via holes to form two pattern marks. A mask is formed over the wafer to cover the insulating layer and the two pattern marks. The mask located above and between the two pattern marks is removed to form a trench exposing the two pattern marks and a portion of the insulating layer. A second conductive layer is formed over the mask to cover the two exposed pattern marks and the exposed insulating layer. The mask and the second conductive layer above the mask are removed simultaneously.
摘要翻译：描述了在晶片上的绝缘层中制造互连的方法。提供其上具有多条导线的晶片。在导线上形成绝缘层。在绝缘层中形成两个通孔，以露出等待修理的两根导电线。将第一导电层填充到通孔中以形成两个图案标记。在晶片上形成掩模以覆盖绝缘层和两个图案标记。去除位于两个图案标记之上和之间的掩模，以形成暴露两个图案标记和绝缘层的一部分的沟槽。在掩模上形成第二导电层以覆盖两个暴露的图案标记和暴露的绝缘层。掩模和掩模上方的第二导电层同时被去除。

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