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1. 发明授权

US5895492A Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system 失效
公开(公告)号：US5895492A
公开(公告)日：1999-04-20
申请号：US864585
申请日：1997-05-28
申请人： Steven Jay Greenspan , Casper Anthony Scalzi , Kenneth Ernest Plambeck
发明人： Steven Jay Greenspan , Casper Anthony Scalzi , Kenneth Ernest Plambeck
IPC分类号： G06F9/46 , G06F12/00
CPC分类号： G06F9/526
摘要： Provides a processor CLE (CPU lock element) for each processor in a protected storage in a multi-processor computer system. Each CLE contains a blocking symbol field (called herein a PLT, program lock token, field), a lock field H, and a wait field W which is used to chain plural CLEs currently having the same blocking symbol. When the lock field H is set to a lock held state, it indicates the associated processor has exclusive rights to access a data resource unit associated with the blocking symbol in the CLE entry. When the wait field in a lock entry contains a pointer to another lock entry and the H field in the lock entry indicates a not held state, the associated processor is waiting for the resource and cannot further execute its PLO instance until it later gets set to the lock state, which is done by the processor of the prior CLE in the chain when it completes execution of its PLO instance. Each PLO instruction also has operand fields, and a function code (FC). The FC controls the manner of processing done by the PLO instance on its operands. Blocking symbols are specified by software to enable the software to utilize hardware enforced serialization of multi-processor accesses simultaneously requested for accessing the same data resource in the computer system. The plural processors may simultaneously, and at any time, initiate PLO instances for the same or different blocking symbols. When different processors simultaneously execute PLO instances having different blocking symbols, the processors may execute in parallel without conflict. But if the different processors simultaneously execute PLO instances having the same blocking symbol, the processors cannot execute in parallel without potential conflict, and the processors must serialize the execution of their PLO instances for accessing the same resource. In the latter case, their CLEs are chained through pointers in wait fields of the CLEs.

2. 发明授权

US5893157A Blocking symbol control in a computer system to serialize accessing a data resource by simultaneous processor requests 失效
标题翻译：阻止计算机系统中的符号控制，以通过同时处理器请求序列化访问数据资源
公开(公告)号：US5893157A
公开(公告)日：1999-04-06
申请号：US864402
申请日：1997-05-28
申请人： Steven Jay Greenspan , Casper Anthony Scalzi , Kenneth Ernest Plambeck
发明人： Steven Jay Greenspan , Casper Anthony Scalzi , Kenneth Ernest Plambeck
IPC分类号： G06F15/16 , G06F9/46 , G06F12/00 , G06F15/177
CPC分类号： G06F9/52
摘要： PLO (perform locked operation) instructions containing blocking symbols are executed on each of multiple processors in a computer system to control coherence in data structures which may be changed by any of multiple processors in a computer system. The blocking symbol is extracted from a PLO instruction instance when invoked by its executing processor. Then the processor hashes the blocking symbol using hardware-microcode (H-M) to generate the location of a lock field in protected storage. The PLO instruction's blocking symbol is associated with a computer resource unit by software providing the PLO instruction, and the blocking symbol then associates the resource with a protected lock through the hashing operation on the blocking symbol. A processor must obtain the lock for a blocking symbol before the executing PLO instruction instance is allowed to make access and change the resource unit associated with the blocking symbol. The blocking symbol controls the PLO operations by serializing simultaneously PLO instruction access requests being made by multiple processors to the same resource unit using the same blocking symbol to allow only one PLO instruction instance to have exclusive access to the resource at a time.
摘要翻译：在计算机系统中的多个处理器中的每一个上执行包含阻塞符号的PLO（执行锁定操作）指令，以控制可由计算机系统中的多个处理器中的任何一个处理器改变的数据结构中的一致性。当由其执行的处理器调用时，从PLO指令实例中提取阻塞符号。然后，处理器使用硬件微码（H-M）对阻塞符号进行散列，以产生受保护存储中锁定字段的位置。 PLO指令的阻塞符号通过提供PLO指令的软件与计算机资源单元相关联，然后阻塞符号通过对阻塞符号的哈希操作将资源与受保护的锁相关联。在允许执行的PLO指令实例进行访问并更改与阻塞符号相关联的资源单元之前，处理器必须获得锁定符号的锁定。阻塞符号通过使用相同的阻塞符号将多个处理器进行的PLO指令访问请求同时序列化到相同的资源单元来控制PLO操作，以允许一次只有一个PLO指令实例对资源进行独占访问。

3. 发明授权

US6128710A Method utilizing a set of blocking-symbol resource-manipulation instructions for protecting the integrity of data in noncontiguous data objects of resources in a shared memory of a multiple processor computer system 失效
标题翻译：利用一组阻塞符号资源操作指令来保护多处理器计算机系统的共享存储器中资源的非连续数据对象中的数据完整性的方法
公开(公告)号：US6128710A
公开(公告)日：2000-10-03
申请号：US92442
申请日：1998-06-05
申请人： Steven Jay Greenspan , Kenneth Ernest Plambeck , Casper Anthony Scalzi
发明人： Steven Jay Greenspan , Kenneth Ernest Plambeck , Casper Anthony Scalzi
IPC分类号： G06F9/46 , G06F9/30
CPC分类号： G06F9/526 , G06F9/52
摘要： Six instructions for the manipulation of discontinuous memory locations in a computer memory are described. They are: Compare and Load (CL), Compare and Swap (CS), Double Compare and Swap (DCS), Compare and Swap and Store (CSST), Compare and Swap and Double Store (CSDST), and Compare and Swap and Triple Store (CSTST). In each instruction a processor associates a programming-specified blocking symbol with a lock not accessible to software. The lock is used by any of these instructions only during its single instance of instruction execution, and the lock is made available (unlocked) at the end of each instance to then enable another blocking-symbol instruction instance to use the lock, thereby serializing concurrent multiple processor requests for accessing the same resource. Programming associates resources in a system with the unique blocking symbols. Each instance of these instructions executes an operand earlier prepared from a data value taken from the resource.. The data value is checked for change during the instance of execution when equality indicates no change since its preparation. These blocking-symbol instructions significantly increase the computer's speed of changing noncontiguous locations in a resource, compared to the time needed by software-protocol locks which must operate over a plurality of instances to make corresponding changes in a resource.
摘要翻译：描述了用于操纵计算机存储器中不连续存储器位置的六个指令。它们是：比较和加载（CL），比较和交换（CS），双重比较和交换（DCS），比较和交换和存储（CSST），比较和交换和双存储（CSDST），以及比较和交换和三重商店（CSTST）。在每个指令中，处理器将编程指定的阻塞符号与软件无法访问的锁相关联。只有在执行指令的单个实例期间，这些指令才被使用，并且锁定在每个实例结束时可用（未锁定），然后允许另一个阻塞符号指令实例使用该锁定，从而序列化并发多个处理器请求访问相同的资源。编程将系统中的资源与唯一的阻塞符号相关联。这些指令的每个实例都执行从资源获取的数据值更早准备的操作数。在执行的实例中检查数据值以进行更改，当相等性表示自其准备以来没有更改。与必须在多个实例上操作以进行资源的相应更改的软件协议锁相比，这些阻塞符号指令显着地增加了计算机改变资源中不连续位置的速度。

4. 发明授权

US5895494A Method of executing perform locked operation instructions for supporting recovery of data consistency if lost due to processor failure, and a method of recovering the data consistency after processor failure 失效
公开(公告)号：US5895494A
公开(公告)日：1999-04-20
申请号：US924890
申请日：1997-09-05
申请人： Casper Anthony Scalzi , Kenneth Ernest Plambeck
发明人： Casper Anthony Scalzi , Kenneth Ernest Plambeck
IPC分类号： G06F11/22 , G06F12/00
CPC分类号： G06F11/2289
摘要： Provides a processor method of executing instances of a Perform Locked Operation (PLO) instruction for enabling a recovery of the consistency of a resource unit being changed by a PLO instance when processor failure occurs anywhere during execution of the PLO instance. The method uses a PLO save area for each processor in a computer system capable of executing PLO instructions. Each PLO save area has a resource-inconsistency (RI) indicator having an RI state and a non-RI state, and stores the function code (FC) of the PLO instance. The RI state indicates that the resource is in a non-usable potentially inconsistent state, and the non-RI state indicates the resource is in the consistent state and may be used. A processor executing a PLO instance writes into its PLO save area all resource addresses where a change is to be made in the resource unit, and also writes in its PLO save area all operand values which will be used to change the resource at the associated addresses. After the processor has successfully written all of these addresses and associated operand data values into its PLO save area, the processor sets its RI indicator to the RI state, and then stores into the resource unit the data values stored in its PLO save area at the resource addresses also stored in its PLO save area, according to the FC also stored therein. After completing all changes in the resource, the processor sets its RI indicator to the non-RI (resource consistent) state. If the processor should ever fail while executing a PLO instance, it signals its failing condition to the system. Then, a RCR method is executed by any operational processor (acting as a RCR processor) to recover the consistency of the resource unit. The RCR method uses the state of the RI indicator with the failed processor's PLO save area, the FC stored therewith, and the content of the failed processor's PLO save area to restore the consistency of the resource unit.

5. 发明授权

US6075937A Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatible instruction emulation 失效
公开(公告)号：US6075937A
公开(公告)日：2000-06-13
申请号：US40671
申请日：1998-03-18
申请人： Casper Anthony Scalzi , Eric Mark Schwarz , William John Starke , James Robert Urquhart , Douglas Wayne Westcott
发明人： Casper Anthony Scalzi , Eric Mark Schwarz , William John Starke , James Robert Urquhart , Douglas Wayne Westcott
IPC分类号： G06F9/455
CPC分类号： G06F9/455
摘要： Preprocessing emulation methods utilizing search argument controls for a template routine address table in a target computing system. Target routines are stored in a target computing system for emulating incompatible instructions of an incompatible architecture which need not be recognized by the architecture of the target computing system. Preprocessing of template routines is preferrably executed on an Auxiliary Emulation Processor (AEP) which may access and patch (modify) some or all of the target instructions in any selected target routine and send them through a queue to a target processor for execution. Execution of the target routines on a target processor emulates the execution of incompatible instructions in an incompatible program in the incompatible architecture. The target processor feeds back results from the execution of target routines to modify any search argument being generated for a currently accessed incompatible instruction to allow the preprocessing selection among multiple target routines for any incompatible instruction currently executing on the target processor to represent any mode or state set by for the incompatible instruction. Another type of feed back from a currently executing target template routine enables non-sequential virtual addressing selection by the preprocessor's access of incompatible instructions during execution of the incompatible program to support incompatible instruction branches and incompatible authority controls. End routine controls are provided in the template routines for feedback synchronization of the accessing of each next incompatible instruction with execution results of each current incompatible instruction having its tempate routine currently executed by the target processor.

6. 发明授权

US6009261A Preprocessing of stored target routines for emulating incompatible instructions on a target processor 失效
标题翻译：用于在目标处理器上模拟不兼容指令的存储目标程序的预处理
公开(公告)号：US6009261A
公开(公告)日：1999-12-28
申请号：US991714
申请日：1997-12-16
申请人： Casper Anthony Scalzi , Eric Mark Schwarz , William John Starke , James Robert Urquhart , Douglas Wayne Westcott
发明人： Casper Anthony Scalzi , Eric Mark Schwarz , William John Starke , James Robert Urquhart , Douglas Wayne Westcott
IPC分类号： G06F9/455
CPC分类号： G06F9/45504
摘要： Provides a program translation and execution method which stores target routines (for execution by a target processor) corresponding to incompatible instructions, interruptions and authorizations of an incompatible program written for execution on another computer system built to a computer architecture incompatible with the architecture of the target processor's computer system. The disclosed process allows the target processor to emulate incompatible acts expected in the operation of an incompatible program when the target processor itself is incapable of performing the emulated acts. Each of the instructions, interruptions and authorizations found in the incompatible programs has one or more corresponding target routines, any of which may need to be preprocessed before it can precisely emulate the execution results required by the incompatible architecture. Target routines (corresponding to the incompatible instruction instances in an incompatible program being emulated) are accessed, patched where necessary, and executed by a target processor to enable the target processor to precisely obtain the execution results of the emulated incompatible program. Before preprocessing, each target routine may not be able to provide identical execution results as required by the incompatible architecture, and the preprocessing may patch one or more of its target instructions to enable the target routine to perform the identical emulation execution of the corresponding incompatible instruction. The patching and other modifications to a target routine are done by one or more preprocessing instructions stored in the target routine.
摘要翻译：提供程序转换和执行方法，其存储对应于不兼容的指令，不兼容程序的中断和授权的对象程序（用于由目标处理器执行），该程序被编写用于在另一个计算机系统上执行以执行，该计算机系统与目标架构不兼容处理器的计算机系统。当目标处理器本身不能执行仿真动作时，所公开的过程允许目标处理器模拟在不兼容的程序的操作中期望的不兼容的动作。在不兼容程序中发现的每个指令，中断和授权都有一个或多个相应的目标程序，其中任何一个可能需要进行预处理，才能精确地模拟不兼容架构所需的执行结果。目标程序（对应于正在仿真的不兼容程序中的不兼容指令实例）被访问，必要时进行修补，并由目标处理器执行，以使目标处理器能够精确获取仿真不兼容程序的执行结果。在预处理之前，每个目标程序可能无法提供与不兼容体系结构相同的执行结果，并且预处理可能会修补其目标指令中的一个或多个，以使目标程序执行相应不兼容指令的相同仿真执行。对目标程序的修补和其他修改由存储在目标程序中的一个或多个预处理指令完成。

7. 发明授权

US5655146A Coexecution processor isolation using an isolation process or having authority controls for accessing system main storage 失效
标题翻译：使用隔离进程执行处理器隔离或具有访问系统主存储的权限控制
公开(公告)号：US5655146A
公开(公告)日：1997-08-05
申请号：US680069
申请日：1996-07-12
申请人： Richard Irwin Baum , Glen Alan Brent , Hatem Mohamed Ghafir , Balakrishna Raghavendra Iyer , Inderpal Singh Narang , Gururaj Seshagiri Rao , Casper Anthony Scalzi , Satya Prakash Sharma , Bhaskar Sinha , Lee Hardy Wilson
发明人： Richard Irwin Baum , Glen Alan Brent , Hatem Mohamed Ghafir , Balakrishna Raghavendra Iyer , Inderpal Singh Narang , Gururaj Seshagiri Rao , Casper Anthony Scalzi , Satya Prakash Sharma , Bhaskar Sinha , Lee Hardy Wilson
IPC分类号： G06F12/10 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/50 , G06F15/16 , G06F15/177 , G06F13/12
CPC分类号： G06F9/5055 , G06F9/3877 , G06F9/3879 , G06F9/5044 , G06F9/547 , G06F2209/509
摘要： A coexecutor for executing functions offloaded from central processors (CPs) in a data processing system, as requested by one or more executing control programs, which include a host operating system (host OS), and subsystem programs and applications executing under the host OS. The offloaded functions are embodied in code modules. Code modules execute in the coexecutor in parallel with non-offloaded functions being executed by the CPs. Thus, the CPs do not need to execute functions which can be executed by the coexecutor. CP requests to the coexecutor specify the code modules which are accessed by the coexecutor from host shared storage under the same constraints and access limitations as the control programs. The coexecutor may emulate host dynamic address translation, and may use a provided host storage key in accessing host storage. The restricted access operating state for the coexecutor maintains data integrity. Coexecutors can be of the same architecture or of a totally different architecture from the CPs to provide an efficient processing environment for the offloaded functions. The coexecutor interfaces host software which provides the requests to the coexecutor. Offloaded modules, once accessed by the coexecutor, may be cached in coexecutor local storage for use by future requests to allow subsequent invocations to proceed without waiting to again load the same module.
摘要翻译：用于执行由数据处理系统中的中央处理器（CP）卸载的执行器，如由一个或多个执行控制程序请求的，其包括主机操作系统（主机OS）以及在主机OS下执行的子系统程序和应用程序。卸载的功能体现在代码模块中。代码模块在执行程序中执行，与CP执行的非卸载函数并行执行。因此，CP不需要执行可由coexecutor执行的功能。向请求者执行的CP请求在与控制程序相同的约束和访问限制下指定由主机共享存储器由coexecutor访问的代码模块。共同执行者可以模拟主机动态地址转换，并且可以使用提供的主机存储密钥来访问主机存储。 coexecutor的受限访问操作状态维护数据完整性。共同执行者可以是与CP相同的架构或与CP完全不同的架构，为卸载的功能提供有效的处理环境。接口主机将向主机提供请求的主机软件。卸载的模块一旦被coexecutor访问，就可以被缓存在coexecutor本地存储器中，供将来的请求使用，以允许后续的调用继续进行，而不用等待再次加载相同的模块。

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