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1. 发明授权

US07664187B2 Memory reduction in digital broadcast receivers 失效
标题翻译：数字广播接收机内存减少
公开(公告)号：US07664187B2
公开(公告)日：2010-02-16
申请号：US11379786
申请日：2006-04-22
申请人： Steven Chen , Howard K. Luu
发明人： Steven Chen , Howard K. Luu
IPC分类号： H04L27/28 , H04J11/00 , G06F15/00
CPC分类号： H04L27/265
摘要： An input random access memory (RAM) module of a fast Fourier transform (FFT) engine of a DVB receiver is used to store, during a first time period, delayed versions of an input signal that includes a first orthogonal frequency division multiplexed (OFDM) symbol and a cyclic prefix therefor received at the receiver, and samples for a second OFDM symbol to be demodulated using the FFT engine during a second time period. Delayed versions of the input signal are stored in the input RAM module of the FFT engine in a first-in-first-out (FIFO) fashion for signal acquisition and for FFT processing. Similarly, an output RAM module of the FFT engine is used to store moving averages of an autocorrelation of the input signal with its cyclic prefix computed over presumed guard intervals and over multiple symbols.
摘要翻译：使用DVB接收机的快速傅立叶变换（FFT）引擎的输入随机存取存储器（RAM）模块在第一时间段期间存储包括第一正交频分复用（OFDM）的输入信号的延迟版本，符号及其循环前缀，并且在第二时间段期间使用FFT引擎解调用于第二OFDM符号的采样。输入信号的延迟版本以先进先出（FIFO）方式存储在FFT引擎的输入RAM模块中，用于信号采集和FFT处理。类似地，FFT引擎的输出RAM模块用于存储输入信号的自相关的运动平均值与其通过推定的保护间隔和多个符号计算的循环前缀。

2. 发明授权

US08819507B2 Field programmable gate arrays with built-in self test mechanisms 有权
标题翻译：具有内置自检机构的现场可编程门阵列
公开(公告)号：US08819507B2
公开(公告)日：2014-08-26
申请号：US12777228
申请日：2010-05-10
申请人： Howard K. Luu , Jackson Y. Chia
发明人： Howard K. Luu , Jackson Y. Chia
IPC分类号： G01R31/28 , G06F11/27 , G01R31/3185
CPC分类号： G06F11/27 , G01R31/318533
摘要： A system and method for designing a field programmable gate array (FPGA) with built-in test mechanism includes several enhancements to traditional circular self-test path (CSTP) BIST architecture. The FPGA BIST scheme isolates primary inputs and primary outputs to improve test coverage. Multiple signature output taps are inserted at CSTP registers throughout the test path to help improve signature aliasing probability. Enhanced CSTP register selection algorithms help prevent register adjacency problems and optimize overall resource utilization for implementation. Multiple clock domains are also handled by the FPGA BIST to allow full chip implementation of the FPGA BIST.
摘要翻译：用于设计具有内置测试机制的现场可编程门阵列（FPGA）的系统和方法包括传统的循环自检路径（CSTP）BIST架构的几项增强功能。 FPGA BIST方案隔离主输入和主输出以提高测试覆盖率。多个签名输出抽头插入到整个测试路径的CSTP寄存器中，以帮助改进签名混叠概率。增强的CSTP寄存器选择算法有助于防止寄存器邻接问题，并优化整体资源的利用。 FPGA BIST还处理多个时钟域，以允许FPGA BIST的全芯片实现。

3. 发明申请

US20110276850A1 Field Programmable Gate Arrays with Built-in Self Test Mechanisms 有权
标题翻译：具有内置自检机构的现场可编程门阵列
公开(公告)号：US20110276850A1
公开(公告)日：2011-11-10
申请号：US12777228
申请日：2010-05-10
申请人： Howard K. Luu , Jackson Y. Chia
发明人： Howard K. Luu , Jackson Y. Chia
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/27 , G01R31/318533
摘要： A system and method for designing a field programmable gate array (FPGA) with built-in test mechanism includes several enhancements to traditional circular self-test path (CSTP) BIST architecture. The FPGA BIST scheme isolates primary inputs and primary outputs to improve test coverage. Multiple signature output taps are inserted at CSTP registers throughout the test path to help improve signature aliasing probability. Enhanced CSTP register selection algorithms help prevent register adjacency problems and optimize overall resource utilization for implementation. Multiple clock domains are also handled by the FPGA BIST to allow full chip implementation of the FPGA BIST.
摘要翻译：用于设计具有内置测试机制的现场可编程门阵列（FPGA）的系统和方法包括传统的循环自检路径（CSTP）BIST架构的几项增强功能。 FPGA BIST方案隔离主输入和主输出以提高测试覆盖率。多个签名输出抽头插入到整个测试路径的CSTP寄存器中，以帮助改进签名混叠概率。增强的CSTP寄存器选择算法有助于防止寄存器邻接问题，并优化整体资源的利用。 FPGA BIST还处理多个时钟域，以允许FPGA BIST的全芯片实现。

4. 发明授权

US07555661B2 Power management in digital receivers that adjusts at least one a of clock rate and a bit width based on received signal 有权
标题翻译：基于接收信号调整至少一个时钟频率和位宽度的数字接收机中的电源管理
公开(公告)号：US07555661B2
公开(公告)日：2009-06-30
申请号：US11381305
申请日：2006-05-02
申请人： Howard K. Luu
发明人： Howard K. Luu
IPC分类号： G06F1/32
CPC分类号： H04L27/2601 , H04L1/0045 , H04L1/0075 , H04L1/203 , H04N21/42607 , H04N21/4436
摘要： Methods and systems consistent with the present invention provide a method for dynamically controlling power consumption in a digital demodulator circuit by varying clock rates and bit widths of demodulator components including an analog to digital converter, decimation filter, OFDM operating engine, FEC decoder, and MPE-FEC processor, according to parameters and conditions of the received signal including modulation mode, signal to noise ratio, effective bit transmission rate, bit error rate, packet error rate, adjacent channel interference, and co-channel interference.
摘要翻译：与本发明一致的方法和系统提供了一种用于通过改变包括模数转换器，抽取滤波器，OFDM操作引擎，FEC解码器和MPE的解调器组件的时钟速率和比特宽度来动态地控制数字解调器电路中的功耗的方法 -FEC处理器，根据接收信号的参数和条件，包括调制模式，信噪比，有效位传输速率，误码率，分组错误率，相邻信道干扰和同信道干扰。

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