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    • 3. 发明授权
    • Distributed digital conferencing system
    • 分布式数字会议系统
    • US4389720A
    • 1983-06-21
    • US256937
    • 1981-04-23
    • Leslie A. BaxterPaul R. BerkowitzClair A. Buzzard
    • Leslie A. BaxterPaul R. BerkowitzClair A. Buzzard
    • H04M3/56H04Q11/04
    • H04Q11/0407H04M3/561
    • In time division communication systems one conference technique is to have a processor combine those samples going to a particular station forming a conference having as many subcombinations as there are stations. This approach, while allowing individual station gain adjustment, suffers from its dependence upon a large number of logic operations for a given conference. A modification of this technique is disclosed which uses a distributed structure such that the individual station ports, under local memory and processor control, operate to combine selected time slot samples into a conference sum unique to the station. In this manner gain values may be assigned on an individual listener station basis while the logic processing for the conference is performed in parallel by the ports involved in the conference.
    • 在时分通信系统中,一种会议技术是使处理器将到达特定站的样本组合成具有与站有多个子组合的会议。 这种方法在允许单独的站增益调整的同时,受到对给定会议的大量逻辑运算的依赖。 公开了该技术的修改,其使用分布式结构,使得在本地存储器和处理器控制下的各个站端口操作以将所选择的时隙样本组合成该站所特有的会议总和。 以这种方式,可以在单个侦听站基础上分配增益值,同时会议的逻辑处理由会议中涉及的端口并行执行。
    • 5. 发明授权
    • Digital loop synchronization circuit
    • 数字环路同步电路
    • US4306304A
    • 1981-12-15
    • US062425
    • 1979-07-31
    • Leslie A. BaxterPeter Cummiskey
    • Leslie A. BaxterPeter Cummiskey
    • H03J3/06H04J3/06H04L7/00H04L7/033H04L12/42H04Q11/04
    • H04L12/422H04J3/0626H04Q11/04
    • There is disclosed a digital loop circuit for controlling synchronization around a closed loop communication system. The control circuit is designed to automatically adjust the delay of the loop to maintain a constant frame bit length without regard to the number of stations connected into the loop. As stations are added or subtracted from the loop, the system operates to add or subtract delay as necessary. A FIFO register having a bit capacity equal to the frame size is inserted serially in the loop and a separate clock is used to control the input and the output of the FIFO register. If a unique frame bit is not received in the anticipated position the output FIFO clock skips one count per frame thereby adding delay to the loop. The loop control circuit operates for situations where the framing bit is on a separate channel and also when the framing bit is on the actual data channel.
    • 公开了一种用于控制围绕闭环通信系统的同步的数字环路电路。 控制电路被设计为自动调整回路的延迟以保持恒定的帧位长度,而不考虑连接到回路中的站数。 由于从循环中添加或减少站,系统将根据需要进行加法或减法延迟。 具有等于​​帧大小的位容量的FIFO寄存器被串行地插入到环路中,并且使用单独的时钟来控制FIFO寄存器的输入和输出。 如果在预期位置没有接收到唯一的帧位,则输出FIFO时钟跳过每帧一个计数,从而将延迟添加到循环。 环路控制电路适用于成帧位在单独信道上的情况,并且当成帧位在实际数据信道上时。
    • 8. 发明授权
    • Digital communication system fault isolation circuit
    • 数字通讯系统故障隔离电路
    • US4279034A
    • 1981-07-14
    • US94494
    • 1979-11-15
    • Leslie A. Baxter
    • Leslie A. Baxter
    • H04B1/74H04L12/437H04Q9/00G08C25/00
    • H04L12/437H04B1/745
    • There is disclosed, for use in a digital communication system, a fault detector circuit operable for removing faulty stations from the system. The disclosed circuit uses a distributed bypass isolation technique and may be used with individual stations or with groups of stations. A multi-bit delay register is connected across each station or station group and the output of the delay register is compared with the output of the parallel stations. When differences in the compared bits are detected the parallel stations are immediately isolated from the system and the bits from the delay register are placed in the system to preserve synchronism. This arrangement has the advantage of allowing immediate corrective action to occur to protect the sanity of the system. In situations where the system is divided into a voice digital bus and a data digital bus different error techniques may be employed for each bus.
    • 公开了一种用于数字通信系统中的故障检测器电路,用于从系统中去除故障站。 所公开的电路使用分布式旁路隔离技术,并且可以与各个站或站的组一起使用。 在每个站或站组之间连接多位延迟寄存器,并将延迟寄存器的输出与并行站的输出进行比较。 当检测到比较位的差异时,并行站立即与系统隔离,并且来自延迟寄存器的位被放置在系统中以保持同步。 这种安排具有允许立即采取纠正措施来保护系统的健全性的优点。 在系统分为语音数字总线和数据总线的情况下,每个总线可以采用不同的错误技术。