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1. 发明授权

US06265273B1 Method of forming rectangular shaped spacers 有权
标题翻译：形成矩形隔片的方法
公开(公告)号：US06265273B1
公开(公告)日：2001-07-24
申请号：US09359502
申请日：1999-07-23
申请人： Steven C. Avanzino , Stephen Keetai Park , Bharath Rangarajan , Jeffrey A. Shields , Larry Yu Wang , Guarionex Morales
发明人： Steven C. Avanzino , Stephen Keetai Park , Bharath Rangarajan , Jeffrey A. Shields , Larry Yu Wang , Guarionex Morales
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/31116
摘要： A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.
摘要翻译：本文公开了一种在集成电路中形成间隔物的方法。该方法包括在半导体衬底上提供栅极结构，在栅极结构的侧面附近沉积间隔物材料，并蚀刻间隔物材料以形成间隔物。间隔物具有暴露于直接溅射的最小表面积。

2. 发明授权

US06265294B1 Integrated circuit having double bottom anti-reflective coating layer 有权
标题翻译：具有双层防反射涂层的集成电路
公开(公告)号：US06265294B1
公开(公告)日：2001-07-24
申请号：US09373084
申请日：1999-08-12
申请人： Stephen Keetai Park , Guarionex Morales , Bharath Rangarajan , Jeff Shields
发明人： Stephen Keetai Park , Guarionex Morales , Bharath Rangarajan , Jeff Shields
IPC分类号： H01L21425
CPC分类号： H01L23/5329 , H01L21/0276 , H01L21/31144 , H01L21/3144 , H01L21/76829 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method reduces the amount of discoloration on interlevel dielectric layers due to anti-reflective coatings (ARC). The invention utilizes a barrier layer, such as, silicon nitride (SiN) that prevents the anti-reflective coating from contacting the interlevel dielectric layer (ILD0). The anti-reflective coating can be silicon oxynitride (SiON) deposited by LPCVD or PECVD.
摘要翻译：制造方法减少了由于抗反射涂层（ARC）引起的层间电介质层上的变色量。本发明利用阻挡层，例如防止抗反射涂层与层间介质层（ILD0）接触的氮化硅（SiN）。抗反射涂层可以是通过LPCVD或PECVD沉积的氮氧化硅（SiON）。

3. 发明授权

US06420104B1 Method of reducing contact size by spacer filling 失效
标题翻译：通过间隔物填充减小接触尺寸的方法
公开(公告)号：US06420104B1
公开(公告)日：2002-07-16
申请号：US09705941
申请日：2000-11-03
申请人： Bharath Rangarajan , Stephen Keetai Park , Guarionex Morales
发明人： Bharath Rangarajan , Stephen Keetai Park , Guarionex Morales
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/76816 , H01L21/76832
摘要： A method of reducing contact size in an integrated circuit includes providing an insulating layer over a semiconductor substrate including a plurality of gate structures, creating an aperture extending through the insulating layer and having side walls, providing a spacer on the side walls of the aperture, and providing a contact in the aperture. The lateral sides of the contact abut the spacer. A contact structure is also disclosed in which a spacer separates a contact from a gate structure to avoid charge gain or loss between the contact and gate structure.
摘要翻译：减小集成电路中的接触尺寸的方法包括在包括多个栅极结构的半导体衬底之上提供绝缘层，形成延伸穿过绝缘层并具有侧壁的孔，在孔的侧壁上提供间隔物，并在孔中提供接触。接触件的侧面靠垫片。还公开了一种接触结构，其中隔离物将接触与栅极结构分离以避免接触和栅极结构之间的电荷增益或损耗。

4. 发明授权

US06287917B1 Process for fabricating an MNOS flash memory device 有权
标题翻译：制造MNOS闪存设备的过程
公开(公告)号：US06287917B1
公开(公告)日：2001-09-11
申请号：US09392675
申请日：1999-09-08
申请人： Stephen Keetai Park , Tim Thurgate , Bharath Rangarajan
发明人： Stephen Keetai Park , Tim Thurgate , Bharath Rangarajan
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A process for fabricating an MNOS device includes the steps of forming a hardmask containing at least first and second openings over a core array area of a semiconductor substrate. An angle doping process is carried out to form halo regions in precise locations within the substrate at the edges of the first and second openings in the hardmask. Another doping process is carried out to form buried bit-lines in the substrate using the hardmask as a doping mask. Once the halo regions and the buried bit-lines are formed, the hardmask is removed and a composite dielectric layer is formed overlying the substrate. A gate layer is deposited to overlie the composite dielectric layer, and an etching process is carried out to form a control gate electrode and a charge storage electrode in the MNOS device
摘要翻译：制造MNOS器件的方法包括以下步骤：在半导体衬底的芯阵列区域上形成至少包含第一和第二开口的硬掩模。进行角度掺杂处理以在硬掩模中的第一和第二开口的边缘处在衬底内的精确位置中形成晕圈。进行另一种掺杂工艺以使用硬掩模作为掺杂掩模在衬底中形成掩埋位线。一旦形成了光晕区域和掩埋位线，就去除了硬掩模，并且在衬底上形成复合介电层。沉积栅极层以覆盖复合介电层，并且进行蚀刻处理以在MNOS器件中形成控制栅电极和电荷存储电极

5. 发明授权

US06771356B1 Scatterometry of grating structures to monitor wafer stress 失效
标题翻译：光栅结构的散射法监测晶片应力
公开(公告)号：US06771356B1
公开(公告)日：2004-08-03
申请号：US10050626
申请日：2002-01-16
申请人： Christopher F. Lyons , Bhanwar Singh , Steven C. Avanzino , Khoi A. Phan , Bharath Rangarajan , Ramkumar Subramanian , Cyrus E. Tabery
发明人： Christopher F. Lyons , Bhanwar Singh , Steven C. Avanzino , Khoi A. Phan , Bharath Rangarajan , Ramkumar Subramanian , Cyrus E. Tabery
IPC分类号： G01B1116
CPC分类号： G01B11/165
摘要： A system for monitoring a fabrication process is provided. The system includes one or more light sources, each light source directing light to one or more gratings on a wafer. Light reflected from the gratings is collected by a measuring system that processes the collected light. The collected light is indicative of distortion due to stress at respective portions of the wafer. The measuring system provides distortion/stress related data to a processor that determines the acceptability of the distortion of the respective portions of the wafer. The collected light may be analyzed by scatterometry systems to produce scatterometry signatures associated with distortion and to produce feed-forward control information that can be employed to control semiconductor fabrication processes.
摘要翻译：提供了一种用于监视制造工艺的系统。该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个光栅。从光栅反射的光被处理收集的光的测量系统收集。所收集的光指示由于晶片的各个部分处的应力引起的变形。测量系统向处理器提供失真/应力相关数据，该处理器确定晶片各部分的失真的可接受性。收集的光可以通过散射测量系统进行分析，以产生与失真相关联的散射仪签名并产生可用于控制半导体制造过程的前馈控制信息。

6. 发明授权

US06702648B1 Use of scatterometry/reflectometry to measure thin film delamination during CMP 有权
标题翻译：在CMP期间使用散射/反射测量薄膜分层
公开(公告)号：US06702648B1
公开(公告)日：2004-03-09
申请号：US10277559
申请日：2002-10-22
申请人： Steven C. Avanzino , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
发明人： Steven C. Avanzino , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： B24B4900
CPC分类号： B24B37/013 , B24B49/12
摘要： One aspect of the present invention relates to a system and method for examining a wafer for delamination in real time while polishing the wafer. The system comprises a polishing system programmed to planarize one or more film layers formed on at least a portion of a semiconductor wafer surface; a real-time metrology system coupled to the polishing system such that the metrology system examines the layers as they are planarized; and one or more delamination sensors, wherein at least a portion of each sensor is integrated into the polishing system in order to provide data to the metrology system and wherein the sensor comprises at least one optical element to detect delamination during polishing. The method involves polishing at least a portion of an uppermost film layer and examining at least a portion of a layer underlying the uppermost film layer for delamination as the uppermost layer is being polished.
摘要翻译：本发明的一个方面涉及一种用于在抛光晶片的同时检查晶片以实时分层的系统和方法。该系统包括被编程为平坦化形成在半导体晶片表面的至少一部分上的一个或多个膜层的抛光系统; 耦合到抛光系统的实时计量系统，使得计量系统在平面化时对层进行检查; 和一个或多个分层传感器，其中每个传感器的至少一部分被集成到抛光系统中，以便向计量系统提供数据，并且其中传感器包括至少一个光学元件以在抛光期间检测分层。该方法包括抛光最上面的薄膜层的至少一部分，并且在最上层被抛光时检查最上面的薄膜层下面的层的至少一部分用于分层。

7. 发明授权

US06684172B1 Sensor to predict void free films using various grating structures and characterize fill performance 失效
标题翻译：传感器预测使用各种光栅结构的无空隙膜，并表征填充性能
公开(公告)号：US06684172B1
公开(公告)日：2004-01-27
申请号：US10034165
申请日：2001-12-27
申请人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
发明人： Ramkumar Subramanian , Steven C. Avanzino , Christopher F. Lyons , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Cyrus E. Tabery
IPC分类号： G01L2500
CPC分类号： C23C16/52 , C23C14/547 , C23C18/1675 , C25D21/12 , H01L21/76877
摘要： One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.
摘要翻译：本发明的一个方面涉及一种金属填充方法及其系统，其涉及在金属化工具中提供具有已知尺寸的多个填充特征的标准校准晶片; 在标准校准晶片上沉积金属材料; 使用传感器系统监测金属材料的沉积，所述传感器系统可操作以测量一个或多个填充过程参数并产生填充过程数据; 控制金属材料的沉积以最小化使用控制系统的空隙形成，其中控制系统从传感器系统接收填充过程数据并分析填充过程数据以产生可操作以控制金属化工具的前馈控制数据; 以及使用由传感器系统和控制系统产生的填充过程数据在金属化工具中的生产晶片上沉积金属材料。本发明还涉及其工具表征过程及其系统。

8. 发明授权

US06562185B2 Wafer based temperature sensors for characterizing chemical mechanical polishing processes 有权
标题翻译：用于表征化学机械抛光工艺的基于晶圆的温度传感器
公开(公告)号：US06562185B2
公开(公告)日：2003-05-13
申请号：US09955552
申请日：2001-09-18
申请人： Steven C. Avanzino , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
发明人： Steven C. Avanzino , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： B24B3700
CPC分类号： B24B37/015
摘要： A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer that has a metal, polysilicon, and/or dielectric layer and/or substrate and a temperature sensor located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a temperature monitoring system that can read the wafer temperature from the temperature sensors and that can analyze the wafer temperature to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer temperature and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer temperature as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties. Such characterization can be employed, for example, to better understand a CMP process, to facilitate initializing subsequent chemical mechanical polishing processes and/or apparatus and/or to control such chemical mechanical polishing processes and/or apparatus by monitoring and/or controlling wafer temperature.
摘要翻译：提供了表征化学机械抛光工艺的系统。该系统包括具有位于金属，多晶硅和/或电介质层和/或衬底中和/或上的金属，多晶硅和/或电介质层和/或衬底和温度传感器的晶片。该系统还包括一个温度监控系统，可以从温度传感器读取晶圆温度，并且可以分析晶圆温度以表征化学机械抛光过程。这种表征包括产生关于晶片温度和抛光速率之间的关系的信息，抛光均匀性和在抛光期间引入缺陷。这些关系与晶片温度相关，如与抛光时间，压力，速度，浆料性质和晶片/金属层性质等参数相关。可以采用这种表征，例如，更好地理解CMP工艺，以便于初始化随后的化学机械抛光工艺和/或设备和/或通过监测和/或控制晶片温度来控制这种化学机械抛光工艺和/或设备。

9. 发明授权

US06934032B1 Copper oxide monitoring by scatterometry/ellipsometry during nitride or BLOK removal in damascene process 有权
标题翻译：在大马士革过程中氮化物或BLOK去除期间通过散射测量/椭偏仪测量氧化铜
公开(公告)号：US06934032B1
公开(公告)日：2005-08-23
申请号：US10261514
申请日：2002-09-30
申请人： Ramkumar Subramanian , Steven C. Avanzino , Bharath Rangarajan , Bhanwar Singh
发明人： Ramkumar Subramanian , Steven C. Avanzino , Bharath Rangarajan , Bhanwar Singh
IPC分类号： C23F4/00 , G01N21/21 , H01L21/311 , G01N21/55 , C23F1/18 , H01L21/66
CPC分类号： H01L21/31116 , C23F4/00 , G01N21/211
摘要： A system and methodology for monitoring and/or controlling a semiconductor fabrication process is disclosed. Scatterometry and/or ellipsometry based techniques can be employed to facilitate providing measurement signals during a damascene phase of the fabrication process. The thickness of layers etched away during the process can be monitored and one or more fabrication components and/or operating parameters associated with the fabrication component(s) can be adjusted in response to the measurements to achieve desired results, such as to mitigate the formation of copper oxide during etching of a copper layer, for example.
摘要翻译：公开了用于监测和/或控制半导体制造工艺的系统和方法。可以采用基于散射法和/或椭偏仪的技术来促进在制造过程的镶嵌阶段期间提供测量信号。可以监测在该过程中被蚀刻掉的层的厚度，并且可以响应于测量来调整与制造部件相关联的一个或多个制造部件和/或操作参数以实现期望的结果，例如减轻形成例如在蚀刻铜层期间的氧化铜。

10. 发明授权

US06808591B1 Model based metal overetch control 有权
标题翻译：基于型号的金属防腐控制
公开(公告)号：US06808591B1
公开(公告)日：2004-10-26
申请号：US10021531
申请日：2001-12-12
申请人： Khoi A. Phan , Bharath Rangarajan , Christopher F. Lyons , Steven C. Avanzino , Ramkumar Subramanian , Bhanwar Singh , Cyrus E. Tabery
发明人： Khoi A. Phan , Bharath Rangarajan , Christopher F. Lyons , Steven C. Avanzino , Ramkumar Subramanian , Bhanwar Singh , Cyrus E. Tabery
IPC分类号： H01L21302
CPC分类号： H01L21/67253 , H01L21/32136
摘要： A systems and methodologies are provided for metal overetch control. Metal overetch processes are controlled by utilizing overetch device models to determine overetch times or overetch endpoints. The systems and methodologies reduce the need for manual testing and manual overetch characterization. An overetch system includes a metal etcher, a target device and an overetch controller. The target device is located in or on the metal etcher. The overetch controller is coupled to the metal etcher. The overetch controller controls overetching of the target device by the metal etcher. The overetch controller includes an overetch time controller, a set of etch control models and a control system.
摘要翻译：提供了用于金属过程控制的系统和方法。通过利用过滤设备模型来确定金属过蚀刻过程以确定过蚀刻时间或过程延伸端点。系统和方法减少了手动测试和手动过程表征的需要。一种过蚀系统包括金属蚀刻机，目标装置和过程控制器。目标设备位于金属蚀刻机中或其上。该过程控制器耦合到金属蚀刻器。过程控制器通过金属蚀刻器控制目标器件的过蚀刻。该过程控制器包括一个过时延时间控制器，一组蚀刻控制模型和一个控制系统。

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