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1. 发明授权

US06184141B2 Method for multiple phase polishing of a conductive layer in a semidonductor wafer 有权
标题翻译：半导体晶片中导电层的多相抛光方法
公开(公告)号：US06184141B2
公开(公告)日：2001-02-06
申请号：US09198369
申请日：1998-11-24
申请人： Steven C. Avanzino , Kashmir S. Sahota , Gerd Marxsen
发明人： Steven C. Avanzino , Kashmir S. Sahota , Gerd Marxsen
IPC分类号： H01L2100
CPC分类号： H01L21/3212
摘要： A method of planarizing a copper containing conductive layer of a semiconductor wafer forms a blanketing copper containing layer within and upon a patterned substrate layer. Chemical mechanical polish (CMP) planarizing is performed on the copper containing layer at a relatively fast rate of removal until most of the layer is removed. The remaining portion of the layer is then CMP planarized at a second rate of removal, which is slower than the first rate of removal, until the copper containing layer is substantially completely removed and a barrier layer underlying the copper containing layer is reached. The multiple phase planarization of the copper containing layer avoids excessive dishing and pattern erosion while maintaining high throughput and uniform removal.
摘要翻译：平面化半导体晶片的含铜导电层的方法在图案化的衬底层的内部和之上形成覆盖铜的层。化学机械抛光（CMP）平面化在含铜层上以相对较快的去除速率进行，直到大部分层被去除。然后将层的剩余部分以第二除去速率平坦化，其比第一脱除速率慢，直到基本上完全除去含铜层，并且到达含铜层下面的阻挡层。含铜层的多相平面化避免了过度的凹陷和图案侵蚀，同时保持了高产量和均匀的去除。

2. 发明申请

US20090061745A1 POLISHING HEAD USING ZONE CONTROL 有权
标题翻译：抛光头使用区域控制
公开(公告)号：US20090061745A1
公开(公告)日：2009-03-05
申请号：US12045273
申请日：2008-03-10
申请人： Jens Heinrich , Gerd Marxsen
发明人： Jens Heinrich , Gerd Marxsen
IPC分类号： B24B5/00 , B24B1/00 , H01L21/302
CPC分类号： B24B37/24 , B24B49/14 , H01L21/3212
摘要： A polishing head for a chemical mechanical polishing apparatus is provided which includes at least two polishing head zones configured to provide different temperatures for transferring heat to at least two zones of a substrate corresponding to the at least two polishing head zones. The present disclosure addresses chemical mechanical polishing which allows a control of the polishing profile even if slurries are used, which show almost no dependency between polishing rate and down force.
摘要翻译：提供了一种用于化学机械抛光装置的抛光头，其包括至少两个抛光头区域，所述至少两个抛光头区域被配置为提供不同的温度，用于将热量传递到对应于所述至少两个抛光头区域的基板的至少两个区域。本公开涉及化学机械抛光，其允许控制抛光轮廓，即使使用浆料，其几乎不显示抛光速率和下压力之间的依赖性。

3. 发明授权

US07268000B2 Method and system for controlling the chemical mechanical polishing of substrates by calculating an overpolishing time and/or a polishing time of a final polishing step 失效
标题翻译：通过计算最终抛光步骤的过度抛光时间和/或抛光时间来控制基板的化学机械抛光的方法和系统
公开(公告)号：US07268000B2
公开(公告)日：2007-09-11
申请号：US10261612
申请日：2002-09-30
申请人： Dirk Wollstein , Jan Raebiger , Gerd Marxsen
发明人： Dirk Wollstein , Jan Raebiger , Gerd Marxsen
IPC分类号： H01L21/00 , H01L21/66
CPC分类号： B24B37/042 , B24B49/03
摘要： A method and a controller for the chemical mechanical polishing (CMP) of substrates and, in particular, for the chemical mechanical polishing of metallization layers is disclosed. In a linear model of the CMP process, the erosion of the metallization layer to be treated is determined by the overpolish time and possibly by an extra polish time on a separate polishing platen for polishing the dielectric layer, wherein the CMP inherent characteristics are represented by sensitivity parameters derived empirically. Moreover, the control operation is designed so that even with a certain inaccuracy of the sensitivity parameters due to subtle process variations, a reasonable controller response is obtained.
摘要翻译：公开了一种用于衬底的化学机械抛光（CMP）的方法和控制器，特别是用于金属化层的化学机械抛光。在CMP工艺的线性模型中，要处理的金属化层的侵蚀由过度抛光时间决定，并且可能通过在用于抛光电介质层的单独抛光台上的额外抛光时间来确定，其中CMP固有特性由灵敏度参数经验性地得出。此外，控制操作被设计为使得即使由于微妙的处理变化而导致的灵敏度参数的一定的不精确性，也可以获得合理的控制器响应。

4. 发明授权

US06774030B2 Method and system for improving the manufacturing of metal damascene structures 失效
标题翻译：改进金属镶嵌结构制造的方法和系统
公开(公告)号：US06774030B2
公开(公告)日：2004-08-10
申请号：US10304904
申请日：2002-11-26
申请人： Gerd Marxsen , Axel Preusse
发明人： Gerd Marxsen , Axel Preusse
IPC分类号： H01L214763
CPC分类号： H01L22/26 , H01L21/3212
摘要： In a method of in situ controlling the degree of fullness of wide lines in a damascene structure, an optical endpoint detection signal is analyzed so as to determine a time interval of substantially constant signal amplitude. The time interval is then used as a measure of the metal filled in a wide line in a damascene structure. By correlating the length of the time interval to at least one process parameter involved in the formation of the damascene structure, the degree of fullness of lines in the damascene structure may be controlled to maintain within a predefined allowable range.
摘要翻译：在现场控制大马士革结构中宽线饱和度的方法中，分析光端点检测信号，以便确定基本恒定的信号幅度的时间间隔。然后将时间间隔用作填充在镶嵌结构中的宽线中的金属的量度。通过将时间间隔的长度与形成镶嵌结构中涉及的至少一个工艺参数相关联，可以控制镶嵌结构中的线的饱和度以保持在预定的允许范围内。

5. 发明授权

US08152595B2 System and method for optical endpoint detection during CMP by using an across-substrate signal 有权
标题翻译：通过使用跨基板信号在CMP期间的光学端点检测的系统和方法
公开(公告)号：US08152595B2
公开(公告)日：2012-04-10
申请号：US12366271
申请日：2009-02-05
申请人： Mike Schlicker , Gerd Marxsen
发明人： Mike Schlicker , Gerd Marxsen
IPC分类号： B24B49/00
CPC分类号： B24B37/013 , B24B49/12 , H01L21/3212
摘要： In a polishing process, the characteristics of the removal process may be monitored at different lateral positions to identify the clearance of the various device regions with a high degree of reliability. Consequently, upon forming sophisticated metallization structures, undue over-polishing may be avoided while at the same time providing reduced leakage currents due to enhanced material removal.
摘要翻译：在抛光过程中，可以在不同的横向位置监视去除过程的特性，以高度可靠地识别各种装置区域的间隙。因此，在形成复杂的金属化结构时，可以避免过度的过度抛光，同时由于增强的材料去除而提供减小的漏电流。

6. 发明申请

US20110186931A1 SEMICONDUCTOR DEVICE FORMED BY A REPLACEMENT GATE APPROACH BASED ON AN EARLY WORK FUNCTION METAL 有权
标题翻译：基于早期工作功能金属的替代门方法形成的半导体器件
公开(公告)号：US20110186931A1
公开(公告)日：2011-08-04
申请号：US12914234
申请日：2010-10-28
申请人： Gerd Marxsen , Joachim Metzger , Robert Binder , Markus Lenski
发明人： Gerd Marxsen , Joachim Metzger , Robert Binder , Markus Lenski
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823857 , H01L29/4966 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66583 , H01L29/7833 , H01L29/7843 , H01L29/7845
摘要： In a replacement gate approach, one work function metal may be provided in an early manufacturing stage, i.e., upon depositing the gate layer stack, thereby reducing the number of deposition steps required in a later manufacturing stage. Consequently, the further work function metal and the electrode metal may be filled into the gate trenches on the basis of superior process conditions compared to conventional replacement gate approaches.
摘要翻译：在替代栅极方法中，可以在早期制造阶段（即，在沉积栅极层堆叠时）提供一个功函数金属，从而减少后续制造阶段所需的沉积步骤的数量。因此，与传统的替代栅极方法相比，基于优越的工艺条件，可以将另外的功函数金属和电极金属填充到栅极沟槽中。

7. 发明申请

US20110076844A1 SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY PERFORMING A POLISHING PROCESS BASED ON A SACRIFICIAL FILL MATERIAL 有权
标题翻译：通过基于真空填充材料执行抛光过程的替代浇口方法中的高级填充条件
公开(公告)号：US20110076844A1
公开(公告)日：2011-03-31
申请号：US12893102
申请日：2010-09-29
申请人： Jens Heinrich , Gerd Marxsen , Katja Steffen
发明人： Jens Heinrich , Gerd Marxsen , Katja Steffen
IPC分类号： H01L21/28
CPC分类号： H01L21/823842 , H01L21/823425 , H01L21/82345 , H01L21/823456 , H01L21/82385 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： In a replacement gate approach, a top area of a gate opening may receive a superior cross-sectional shape after the deposition of a work function adjusting species on the basis of a polishing process, wherein a sacrificial material may protect the sensitive materials in the gate opening.
摘要翻译：在替代浇口方法中，在沉积根据抛光工艺调节物质的功函数之后，栅极开口的顶部区域可以接收优异的横截面形状，其中牺牲材料可以保护栅极中的敏感材料开放

8. 发明授权

US06958247B2 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process 失效
标题翻译：在图案化电介质层上电镀铜的方法，以提高后续CMP工艺的工艺均匀性
公开(公告)号：US06958247B2
公开(公告)日：2005-10-25
申请号：US10666195
申请日：2003-09-19
申请人： Gerd Marxsen , Axel Preusse , Markus Nopper , Frank Mauersberger
发明人： Gerd Marxsen , Axel Preusse , Markus Nopper , Frank Mauersberger
IPC分类号： H01L21/288 , H01L21/768 , H01L21/461 , H01L21/4763
CPC分类号： H01L21/2885 , H01L21/7684 , H01L21/76877
摘要： In a new method of plating metal onto dielectric layers including small diameter vias and large diameter trenches, a surface roughness is created at least on non-patterned regions of the dielectric layer to enhance the uniformity of material removal in a subsequent chemical mechanical polishing (CMP) process.
摘要翻译：在将金属电镀到包括小直径通孔和大直径沟槽的电介质层上的新方法中，至少在电介质层的非图案化区域上产生表面粗糙度，以增强后续化学机械抛光（CMP）中材料去除的均匀性）过程。

9. 发明授权

US08183139B2 Reduced defectivity in contacts of a semiconductor device comprising replacement gate electrode structures by using an intermediate cap layer 有权
标题翻译：通过使用中间盖层，减少包括替换栅电极结构的半导体器件的触点的缺陷
公开(公告)号：US08183139B2
公开(公告)日：2012-05-22
申请号：US12963908
申请日：2010-12-09
申请人： Gerd Marxsen , Jens Heinrich
发明人： Gerd Marxsen , Jens Heinrich
IPC分类号： H01L21/28
CPC分类号： H01L21/76802 , H01L21/31144 , H01L29/66545
摘要： Superior contact elements may be formed in semiconductor devices in which sophisticated replacement gate approaches may be applied. To this end, a dielectric cap layer is provided prior to patterning the interlayer dielectric material so that any previously created cracks may be reliably sealed prior to the deposition of the contact material, while the removal of any excess portion thereof may be performed without an undue interaction with the electrode metal of the gate electrode structures. Consequently, a significantly reduced defect rate may be achieved.
摘要翻译：可以在其中可以应用复杂的替代栅极方法的半导体器件中形成优良的接触元件。为此，在图案化层间电介质材料之前提供电介质盖层，使得任何先前产生的裂纹可以在接触材料沉积之前被可靠地密封，同时可以在没有不适当的情况下执行任何多余部分的去除与栅电极结构的电极金属的相互作用。因此，可以实现显着降低的缺陷率。

10. 发明申请

US20110269303A1 Reduced Defectivity in Contacts of a Semiconductor Device Comprising Replacement Gate Electrode Structures by Using an Intermediate Cap Layer 有权
标题翻译：通过使用中间盖层减少包括替代栅电极结构的半导体器件的触点的缺陷
公开(公告)号：US20110269303A1
公开(公告)日：2011-11-03
申请号：US12963908
申请日：2010-12-09
申请人： Gerd Marxsen , Jens Heinrich
发明人： Gerd Marxsen , Jens Heinrich
IPC分类号： H01L21/28
CPC分类号： H01L21/76802 , H01L21/31144 , H01L29/66545
摘要： Superior contact elements may be formed in semiconductor devices in which sophisticated replacement gate approaches may be applied. To this end, a dielectric cap layer is provided prior to patterning the interlayer dielectric material so that any previously created cracks may be reliably sealed prior to the deposition of the contact material, while the removal of any excess portion thereof may be performed without an undue interaction with the electrode metal of the gate electrode structures. Consequently, a significantly reduced defect rate may be achieved.
摘要翻译：可以在其中可以应用复杂的替代栅极方法的半导体器件中形成优良的接触元件。为此，在图案化层间电介质材料之前提供电介质盖层，使得任何先前产生的裂纹可以在接触材料沉积之前被可靠地密封，同时可以在没有不适当的情况下执行任何多余部分的去除与栅电极结构的电极金属的相互作用。因此，可以实现显着降低的缺陷率。

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