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1. 发明授权

US07220642B2 Protection of active layers of memory cells during processing of other elements 有权
标题翻译：在处理其他元件期间保护存储器单元的有源层
公开(公告)号：US07220642B2
公开(公告)日：2007-05-22
申请号：US10987262
申请日：2004-11-12
申请人： Steven Avanzino , Igor Sokolik , Suzette Pangrle , Nicholas H. Tripsas , Jeffrey Shields
发明人： Steven Avanzino , Igor Sokolik , Suzette Pangrle , Nicholas H. Tripsas , Jeffrey Shields
IPC分类号： H01L21/336
CPC分类号： H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： A method of fabricating an electronic structure by providing a conductive layer, providing a dielectric layer over the conductive layer, providing first and second openings through the dielectric layer, providing first and second conductive bodies in the first and second openings respectively and in contact with the conductive layer, providing a memory structure over the first conductive body, providing a protective element over the memory structure, and undertaking processing on the second conductive body.
摘要翻译：一种通过提供导电层制造电子结构的方法，在导电层上提供电介质层，提供通过介电层的第一和第二开口，分别在第一和第二开口中提供第一和第二导电体，并与在第一导电体上提供存储结构，在存储器结构上提供保护元件，并对第二导电体进行处理。

2. 发明申请

US20060102887A1 Protection of active layers of memory cells during processing of other elements 有权
标题翻译：在处理其他元件期间保护存储器单元的有源层
公开(公告)号：US20060102887A1
公开(公告)日：2006-05-18
申请号：US10987262
申请日：2004-11-12
申请人： Steven Avanzino , Igor Sokolik , Suzette Pangrle , Nicholas Tripsas , Jeffrey Shields
发明人： Steven Avanzino , Igor Sokolik , Suzette Pangrle , Nicholas Tripsas , Jeffrey Shields
IPC分类号： H01L29/02
CPC分类号： H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： A method of fabricating an electronic structure by providing a conductive layer, providing a dielectric layer over the conductive layer, providing first and second openings through the dielectric layer, providing first and second conductive bodies in the first and second openings respectively and in contact with the conductive layer, providing a memory structure over the first conductive body, providing a protective element over the memory structure, and undertaking processing on the second conductive body.
摘要翻译：一种通过提供导电层制造电子结构的方法，在导电层上提供电介质层，提供通过介电层的第一和第二开口，分别在第一和第二开口中提供第一和第二导电体，并与在第一导电体上提供存储结构，在存储器结构上提供保护元件，并对第二导电体进行处理。

3. 发明授权

US07035141B1 Diode array architecture for addressing nanoscale resistive memory arrays 有权
标题翻译：用于寻址纳米尺度电阻式存储器阵列的二极管阵列架构
公开(公告)号：US07035141B1
公开(公告)日：2006-04-25
申请号：US10990706
申请日：2004-11-17
申请人： Nicholas H. Tripsas , Colin S. Bill , Michael A. VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Daisy Cai , Suzette Pangrle , Steven Avanzino
发明人： Nicholas H. Tripsas , Colin S. Bill , Michael A. VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Daisy Cai , Suzette Pangrle , Steven Avanzino
IPC分类号： G11C11/36 , G11C27/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages.
摘要翻译：本存储器结构包括第一导体，第二导体，连接到第二导体的电阻性存储单元，连接到电阻存储单元和第一导体的第一二极管，并且从电阻存储单元向前取向所述第一导体和连接到所述电阻性存储器单元和所述第一导体的第二二极管与所述第一二极管并联，并且在从所述电阻存储器单元到所述第一导体的相反方向上定向。第一和第二二极管具有不同的阈值电压。

4. 发明授权

US07391064B1 Memory device with a selection element and a control line in a substantially similar layer 有权
标题翻译：具有选择元件和控制线的存储器件在基本相似的层中
公开(公告)号：US07391064B1
公开(公告)日：2008-06-24
申请号：US11001519
申请日：2004-12-01
申请人： Nicholas H. Tripsas , Suzette Pangrle
发明人： Nicholas H. Tripsas , Suzette Pangrle
IPC分类号： H01L29/80
CPC分类号： H01L27/1021 , H01L27/101
摘要： The invention facilitates manufacture of semiconductor memory components by reducing the number of layers required to implement a semiconductor memory device. The invention provides for a selection element to be formed in the same layer as one of the control lines (e.g. one of the wordline and bitline). In one embodiment of the invention, a diode is implemented as the selection element within the same layer as one of the control lines. Production of the selection element within the same layer as one of the wordline and bitline reduces problems associated with vertical stacking, increases device yield and reduces related production costs. The invention also provides an efficient method of producing memory devices with the selection element in the same layer as one of the control lines.
摘要翻译：本发明有利于通过减少实现半导体存储器件所需的层数来制造半导体存储器组件。本发明提供了一种选择元件，其形成在与控制线之一（例如字线和位线之一）相同的层中。在本发明的一个实施例中，二极管被实现为与控制线之一在同一层内的选择元件。生产作为字线和位线之一的同一层内的选择元件可减少与垂直堆叠相关的问题，提高了设备产量并降低了相关生产成本。本发明还提供了一种生产存储器件的有效方法，其中选择元件与控制线之一在同一层中。

5. 发明申请

US20070007585A1 Memory device with improved data retention 审中-公开
标题翻译：具有改善数据保留性能的内存设备
公开(公告)号：US20070007585A1
公开(公告)日：2007-01-11
申请号：US11174861
申请日：2005-07-05
申请人： Igor Sokolik , Richard Kingsborough , David Gaun , Swaroop Kaza , Stuart Spitzer , Suzette Pangrle
发明人： Igor Sokolik , Richard Kingsborough , David Gaun , Swaroop Kaza , Stuart Spitzer , Suzette Pangrle
IPC分类号： H01L29/792
CPC分类号： G11C13/0016 , B82Y10/00 , G11C13/0014 , G11C2213/11 , G11C2213/56
摘要： The present memory device includes first and second electrodes, a passive layer between the first and second electrodes and an active layer between the first and second electrodes, the active layer being of a material containing randomly oriented pores which are interconnected to form passages through the active layer.
摘要翻译：本存储器件包括第一和第二电极，第一和第二电极之间的无源层和第一和第二电极之间的有源层，活性层是含有随机取向的孔的材料，其互连以形成通过活性物质的通道层。

6. 发明授权

US07102156B1 Memory elements using organic active layer 有权
标题翻译：记忆元素使用有机活性层
公开(公告)号：US07102156B1
公开(公告)日：2006-09-05
申请号：US11021681
申请日：2004-12-23
申请人： Richard Kingsborough , Igor Sokolik , David Gaun , Swaroop Kaza , Suzette Pangrle , Alexander Nickel , Stuart Spitzer
发明人： Richard Kingsborough , Igor Sokolik , David Gaun , Swaroop Kaza , Suzette Pangrle , Alexander Nickel , Stuart Spitzer
IPC分类号： H01L35/24 , H01L51/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L27/285 , H01L51/0036 , H01L51/0039 , H01L51/0043
摘要： A memory element includes a first electrode, a passive layer on and in contact with the first electrode, a polyfluorene active layer on and in contact with the active layer, and a second electrode on and in contact with the polyfluorene active layer. The chemical structure of the polyfluorene active layer may be altered to take different forms, each providing a different memory element operating characteristic.
摘要翻译：存储元件包括第一电极，与第一电极接触并与第一电极接触的钝化层，与活性层接触并与活性层接触的聚芴有源层，以及与聚芴活性层接触并与其接触的第二电极。可以改变聚芴有源层的化学结构以采取不同的形式，每种形式提供不同的存储元件操作特性。

7. 发明申请

US20070090343A1 System and method for processing an organic memory cell 有权
标题翻译：用于处理有机存储单元的系统和方法
公开(公告)号：US20070090343A1
公开(公告)日：2007-04-26
申请号：US11256558
申请日：2005-10-21
申请人： Nicolay Yudanov , Igor Sokolik , Richard Kingsborough , William Leonard , Suzette Pangrle , Nicholas Tripsas , Minh Ngo
发明人： Nicolay Yudanov , Igor Sokolik , Richard Kingsborough , William Leonard , Suzette Pangrle , Nicholas Tripsas , Minh Ngo
IPC分类号： H01L29/08
CPC分类号： H01L51/001 , C23C16/54 , H01J2237/3321 , H01L27/285
摘要： A system and method are disclosed for processing an organic memory cell. An exemplary system can employ an enclosed processing chamber, a passive layer formation component operative to form a passive layer on a first electrode, and an organic semiconductor layer formation component operative to form an organic semiconductor layer on the passive layer. A wafer substrate is not needed to transfer from a passive layer formation system to an organic semiconductor layer formation system. The passive layer is not exposed to air after formation of the passive layer and before formation of the organic semiconductor layer. As a result, conductive impurities caused by the exposure to air do not occur in the thin film layer, thus improving productivity, quality, and reliability of organic memory devices. The system can further employ a second electrode formation component operative to form a second electrode on the organic semiconductor layer.
摘要翻译：公开了一种用于处理有机存储单元的系统和方法。示例性系统可以采用封闭的处理室，可操作以在第一电极上形成钝化层的无源层形成部件和可操作地在被动层上形成有机半导体层的有机半导体层形成部件。晶片衬底不需要从钝化层形成系统转移到有机半导体层形成系统。钝化层在形成无源层之后并且在形成有机半导体层之前不暴露于空气。结果，在薄膜层中不会发生由暴露于空气引起的导电杂质，从而提高了有机存储器件的生产率，质量和可靠性。该系统可以进一步采用可在有机半导体层上形成第二电极的第二电极形成部件。

8. 发明申请

US20070007510A1 Stackable memory device and organic transistor structure 审中-公开
标题翻译：可堆叠存储器件和有机晶体管结构
公开(公告)号：US20070007510A1
公开(公告)日：2007-01-11
申请号：US11174881
申请日：2005-07-05
申请人： Igor Sokolik , Suzette Pangrle , Juri Krieger
发明人： Igor Sokolik , Suzette Pangrle , Juri Krieger
IPC分类号： H01L29/08
CPC分类号： H01L51/0541 , H01L27/0688 , H01L27/281 , H01L27/283
摘要： In the present electronic structure, a first electronic device includes a first pair of electrodes and an active layer between the first pair of electrodes. An organic transistor is made up of organic material, a source, a drain, and a gate, one of the first pair of electrodes being connected to one of the source and drain of the organic transistor. A second electronic device includes a second pair of electrodes and an active layer between the second pair of electrodes, one of the second pair of electrodes being in contact with an insulating body adjacent the organic transistor.
摘要翻译：在本电子结构中，第一电子器件包括第一对电极和第一对电极之间的有源层。有机晶体管由有机材料，源极，漏极和栅极组成，第一对电极之一连接到有机晶体管的源极和漏极之一。第二电子器件包括第二对电极和在第二对电极之间的有源层，第二对电极中的一个与邻近有机晶体管的绝缘体接触。

9. 发明申请

US20060104111A1 DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY ARRAYS 有权
标题翻译：用于解决纳米电阻记忆阵列的二极体阵列
公开(公告)号：US20060104111A1
公开(公告)日：2006-05-18
申请号：US10990706
申请日：2004-11-17
申请人： Nicholas Tripsas , Colin Bill , Michael VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Cai , Suzette Pangrle , Steven Avanzino
发明人： Nicholas Tripsas , Colin Bill , Michael VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Cai , Suzette Pangrle , Steven Avanzino
IPC分类号： G11C11/36
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages
摘要翻译：本存储器结构包括第一导体，第二导体，连接到第二导体的电阻性存储单元，连接到电阻存储单元和第一导体的第一二极管，并且从电阻存储单元向前取向所述第一导体和连接到所述电阻性存储器单元和所述第一导体的第二二极管与所述第一二极管并联，并且在从所述电阻存储器单元到所述第一导体的相反方向上定向。第一和第二二极管具有不同的阈值电压

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