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1. 发明申请

US20070012982A1 Multipurpose metal fill 审中-公开
标题翻译：多功能金属填充
公开(公告)号：US20070012982A1
公开(公告)日：2007-01-18
申请号：US11526790
申请日：2006-09-25
申请人： Stephen Wu , Ernie Geronaga
发明人： Stephen Wu , Ernie Geronaga
IPC分类号： H01L29/94
CPC分类号： H01L29/94
摘要： The present invention adds a plurality of substrate barriers for reducing substrate noise. The barriers, consisting of a plurality of equally sized n-well regions formed within the p-substrate, are formed between the analog and digital portions and on at least one side of sensitive analog circuits. A MOSFET transistor configured as a capacitor is formed within each of the n-well regions and is coupled between supply and circuit common to filter supply noise. A metal layer capacitor is formed above each MOSFET capacitor and is coupled between supply and circuit common. The present inventive circuit adds metallization to satisfy metal percentage requirements and to improve noise filtering. Each barrier region includes a plurality of coupled (shorted) n-wells with MOSFET transistors configured as capacitors. Additionally, in the described embodiment, the metallization layer is formed to create metal capacitors on top layers of the n-well regions to create additional noise filtering between supply and ground.
摘要翻译：本发明增加了用于降低衬底噪声的多个衬底屏障。在模拟和数字部分之间以及在敏感的模拟电路的至少一侧上形成由p型衬底内形成的多个相同大小的n阱区组成的势垒。配置为电容器的MOSFET晶体管形成在每个n阱区域中，并且耦合在电源和电路之间，以滤除电源噪声。在每个MOSFET电容器上方形成一个金属层电容器，并在电源和电路之间耦合。本发明的电路增加了金属化以满足金属百分比要求并改善噪声过滤。每个屏障区域包括多个被配置为电容器的MOSFET晶体管的耦合（短路）n阱。另外，在所描述的实施例中，形成金属化层以在n阱区域的顶层上形成金属电容器，以在电源和地之间产生额外的噪声滤波。

2. 发明授权

US07112838B2 Multipurpose metal fill 失效
标题翻译：多功能金属填充
公开(公告)号：US07112838B2
公开(公告)日：2006-09-26
申请号：US10814421
申请日：2004-03-31
申请人： Stephen Wu , Ernie Geronaga
发明人： Stephen Wu , Ernie Geronaga
IPC分类号： H01L29/92
CPC分类号： H01L29/94
摘要： The present invention adds a plurality of substrate barriers for reducing substrate noise. The barriers, consisting of a plurality of equally sized n-well regions formed within the p-substrate, are formed between the analog and digital portions and on at least one side of sensitive analog circuits. A MOSFET transistor configured as a capacitor is formed within each of the n-well regions and is coupled between supply and circuit common to filter supply noise. A metal layer capacitor is formed above each MOSFET capacitor and is coupled between supply and circuit common. The present inventive circuit adds metallization to satisfy metal percentage requirements and to improve noise filtering. Each barrier region includes a plurality of coupled (shorted) n-wells with MOSFET transistors configured as capacitors. Additionally, in the described embodiment, the metallization layer is formed to create metal capacitors on top layers of the n-well regions to create additional noise filtering between supply and ground.
摘要翻译：本发明增加了用于降低衬底噪声的多个衬底屏障。在模拟和数字部分之间以及在敏感的模拟电路的至少一侧上形成由p型衬底内形成的多个相同大小的n阱区组成的势垒。配置为电容器的MOSFET晶体管形成在每个n阱区域中，并且耦合在电源和电路之间，以滤除电源噪声。在每个MOSFET电容器上方形成一个金属层电容器，并在电源和电路之间耦合。本发明的电路增加了金属化以满足金属百分比要求并改善噪声过滤。每个屏障区域包括多个被配置为电容器的MOSFET晶体管的耦合（短路）n阱。另外，在所描述的实施例中，形成金属化层以在n阱区域的顶层上形成金属电容器，以在电源和地之间产生额外的噪声滤波。

3. 发明申请

US20050224885A1 Multipurpose metal fill 失效
标题翻译：多功能金属填充
公开(公告)号：US20050224885A1
公开(公告)日：2005-10-13
申请号：US10814421
申请日：2004-03-31
申请人： Stephen Wu , Ernie Geronaga
发明人： Stephen Wu , Ernie Geronaga
IPC分类号： H01L29/06 , H01L29/94
CPC分类号： H01L29/94
摘要： The present invention adds a plurality of substrate barriers for reducing substrate noise. The barriers, consisting of a plurality of equally sized n-well regions formed within the p-substrate, are formed between the analog and digital portions and on at least one side of sensitive analog circuits. A MOSFET transistor configured as a capacitor is formed within each of the n-well regions and is coupled between supply and circuit common to filter supply noise. A metal layer capacitor is formed above each MOSFET capacitor and is coupled between supply and circuit common. The present inventive circuit adds metallization to satisfy metal percentage requirements and to improve noise filtering. Each barrier region includes a plurality of coupled (shorted) n-wells with MOSFET transistors configured as capacitors. Additionally, in the described embodiment, the metallization layer is formed to create metal capacitors on top layers of the n-well regions to create additional noise filtering between supply and ground.
摘要翻译：本发明增加了用于降低衬底噪声的多个衬底屏障。在模拟和数字部分之间以及在敏感的模拟电路的至少一侧上形成由p型衬底内形成的多个相同大小的n阱区组成的势垒。配置为电容器的MOSFET晶体管形成在每个n阱区域中，并且耦合在电源和电路之间，以滤除电源噪声。在每个MOSFET电容器上方形成一个金属层电容器，并在电源和电路之间耦合。本发明的电路增加了金属化以满足金属百分比要求并改善噪声过滤。每个屏障区域包括多个被配置为电容器的MOSFET晶体管的耦合（短路）n阱。另外，在所描述的实施例中，形成金属化层以在n阱区域的顶层上形成金属电容器，以在电源和地之间产生额外的噪声滤波。

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