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1. 发明申请

US20120199941A1 SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL) 有权
标题翻译：应力衬里上的硅半导体器件（SOL）
公开(公告)号：US20120199941A1
公开(公告)日：2012-08-09
申请号：US13365764
申请日：2012-02-03
申请人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
发明人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
IPC分类号： H01L29/06
CPC分类号： H01L29/66477 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/6653 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/7843 , H01L29/7849
摘要： A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.
摘要翻译：公开了一种制造集成电路的方法和在应力衬垫上具有硅的集成电路。在一个实施例中，该方法包括提供包括嵌入式一次性层的半导体衬底，以及去除该一次性层的至少一部分以在衬底内形成空隙。该方法还包括在该空隙中沉积材料以形成应力衬垫，以及在衬底的外部半导体层上形成晶体管。该半导体层将晶体管与应力衬垫分开。在一个实施例中，衬底包括隔离区; 并且所述去除包括在所述隔离区域中形成凹部，以及经由所述凹部去除所述一次性层的至少一部分。在一个实施例中，沉积包括通过凹部将材料沉积在空隙中。端盖可以形成在应力衬垫的端部处的凹部中。

2. 发明授权

US08399933B2 Semiconductor device having silicon on stressed liner (SOL) 有权
标题翻译：在应力衬垫（SOL）上具有硅的半导体器件
公开(公告)号：US08399933B2
公开(公告)日：2013-03-19
申请号：US13365764
申请日：2012-02-03
申请人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
发明人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66477 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/6653 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/7843 , H01L29/7849
摘要： A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.
摘要翻译：公开了一种制造集成电路的方法和在应力衬垫上具有硅的集成电路。在一个实施例中，该方法包括提供包括嵌入式一次性层的半导体衬底，以及去除该一次性层的至少一部分以在衬底内形成空隙。该方法还包括在该空隙中沉积材料以形成应力衬垫，以及在衬底的外部半导体层上形成晶体管。该半导体层将晶体管与应力衬垫分开。在一个实施例中，衬底包括隔离区; 并且所述去除包括在所述隔离区域中形成凹部，以及经由所述凹部去除所述一次性层的至少一部分。在一个实施例中，沉积包括通过凹部将材料沉积在空隙中。端盖可以形成在应力衬垫的端部处的凹部中。

3. 发明授权

US08138523B2 Semiconductor device having silicon on stressed liner (SOL) 有权
标题翻译：在应力衬垫（SOL）上具有硅的半导体器件
公开(公告)号：US08138523B2
公开(公告)日：2012-03-20
申请号：US12575962
申请日：2009-10-08
申请人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
发明人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
IPC分类号： H01L21/8238
CPC分类号： H01L29/66477 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/6653 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/7843 , H01L29/7849
摘要： A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.
摘要翻译：公开了一种制造集成电路的方法和在应力衬垫上具有硅的集成电路。在一个实施例中，该方法包括提供包括嵌入式一次性层的半导体衬底，以及去除该一次性层的至少一部分以在衬底内形成空隙。该方法还包括在该空隙中沉积材料以形成应力衬垫，以及在衬底的外部半导体层上形成晶体管。该半导体层将晶体管与应力衬垫分开。在一个实施例中，衬底包括隔离区; 并且所述去除包括在所述隔离区域中形成凹部，以及经由所述凹部去除所述一次性层的至少一部分。在一个实施例中，沉积包括通过凹部将材料沉积在空隙中。端盖可以形成在应力衬垫的端部处的凹部中。

4. 发明申请

US20110084315A1 SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL) 有权
标题翻译：应力衬里上的硅半导体器件（SOL）
公开(公告)号：US20110084315A1
公开(公告)日：2011-04-14
申请号：US12575962
申请日：2009-10-08
申请人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
发明人： Stephen W. Bedell , Josephine B. Chang , Chung-Hsun Lin
IPC分类号： H01L27/08 , H01L21/30
CPC分类号： H01L29/66477 , H01L21/8238 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/6653 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/7843 , H01L29/7849
摘要： A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.
摘要翻译：公开了一种制造集成电路的方法和在应力衬垫上具有硅的集成电路。在一个实施例中，该方法包括提供包括嵌入式一次性层的半导体衬底，以及去除该一次性层的至少一部分以在衬底内形成空隙。该方法还包括在该空隙中沉积材料以形成应力衬垫，以及在衬底的外部半导体层上形成晶体管。该半导体层将晶体管与应力衬垫分开。在一个实施例中，衬底包括隔离区; 并且所述去除包括在所述隔离区域中形成凹部，以及经由所述凹部去除所述一次性层的至少一部分。在一个实施例中，沉积包括通过凹部将材料沉积在空隙中。端盖可以形成在应力衬垫的端部处的凹部中。

5. 发明授权

US08669167B1 Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices 有权
标题翻译：金属门功能工程技术可实现多个阈值电压FINFET器件
公开(公告)号：US08669167B1
公开(公告)日：2014-03-11
申请号：US13596687
申请日：2012-08-28
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/092
CPC分类号： H01L27/1211 , H01L21/845
摘要： Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a FIN FET device includes the following steps. A SOI wafer having a SOI layer over a BOX is provided. An oxide layer is formed over the SOI layer. A plurality of fins is patterned in the SOI layer and the oxide layer. An interfacial oxide is formed on the fins. A conformal gate dielectric layer, a conformal gate metal layer and a conformal work function setting material layer are deposited on the fins. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer deposited over the fins is proportional to a pitch of the fins. A FIN FET device is also provided.
摘要翻译：在Fin FET器件中提供栅极功能工程的技术，其功能设定材料的数量与翅片间距成正比。一方面，制造FIN FET器件的方法包括以下步骤。提供了在BOX上具有SOI层的SOI晶片。在SOI层上形成氧化物层。在SOI层和氧化物层中图案化多个翅片。翅片上形成界面氧化物。共形栅介电层，共形栅极金属层和共形功函数设定材料层沉积在散热片上。共形栅极金属层的体积和沉积在鳍片上的共形功函数设定材料层的体积与翅片的间距成正比。还提供了一种FIN FET器件。

6. 发明申请

US20140051213A1 Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices 有权
标题翻译：金属栅极工作功能工程技术开启多阈值电压纳米线FET器件
公开(公告)号：US20140051213A1
公开(公告)日：2014-02-20
申请号：US13588724
申请日：2012-08-17
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L29/16 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/4232 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method of fabricating a nanowire FET device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are etched in the SOI layer. The nanowires are suspended over the BOX. An interfacial oxide is formed surrounding each of the nanowires. A conformal gate dielectric is deposited on the interfacial oxide. A conformal first gate material is deposited on the conformal gate dielectric. A work function setting material is deposited on the conformal first gate material. A second gate material is deposited on the work function setting material to form at least one gate stack over the nanowires. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.
摘要翻译：制造纳米线FET器件的方法包括以下步骤。提供了具有在BOX上的SOI层的SOI晶片。在SOI层中蚀刻纳米线和焊盘。纳米线悬挂在BOX上。围绕每个纳米线形成界面氧化物。共形栅电介质沉积在界面氧化物上。保形第一栅极材料沉积在保形栅极电介质上。工件功能设定材料沉积在保形第一栅极材料上。第二栅极材料沉积在功函数设定材料上以在纳米线上形成至少一个栅叠层。栅极堆叠中的共形第一栅极材料的体积和/或功函数设定材料的体积与纳米线的间距成比例。

7. 发明申请

US20140048882A1 TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES 有权
标题翻译：门工功能工程技术降低平面CMOS器件中的短路通道效应
公开(公告)号：US20140048882A1
公开(公告)日：2014-02-20
申请号：US13617283
申请日：2012-09-14
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/1203
摘要： In one aspect, a CMOS device is provided. The CMOS device includes a SOI wafer having a SOI layer over a BOX; one or more active areas formed in the SOI layer in which one or more FET devices are formed, each of the FET devices having an interfacial oxide on the SOI layer and a gate stack on the interfacial oxide layer, the gate stack having (i) a conformal gate dielectric layer present on a top and sides of the gate stack, (ii) a conformal gate metal layer lining the gate dielectric layer, and (iii) a conformal workfunction setting metal layer lining the conformal gate metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer present in the gate stack are/is proportional to a length of the gate stack.
摘要翻译：在一个方面，提供一种CMOS器件。 CMOS器件包括在BOX上具有SOI层的SOI晶片; 形成在其中形成有一个或多个FET器件的SOI层中的一个或多个有源区，每个FET器件在SOI层上具有界面氧化物，在界面氧化物层上具有栅极堆叠，所述栅极堆叠具有（i）存在于栅极堆叠的顶部和侧面上的共形栅极电介质层，（ii）衬在栅极介电层的共形栅极金属层，以及（iii）在保形栅极金属层之上的共形功函数设定金属层。存在于栅极堆叠中的共形栅极金属层的体积和/或共形功函数设定金属层的体积与栅极堆叠的长度成比例。

8. 发明申请

US20130256797A1 Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure 有权
标题翻译：通过使用可变间距门形成的非对称FET用作逻辑器件和测试结构
公开(公告)号：US20130256797A1
公开(公告)日：2013-10-03
申请号：US13441048
申请日：2012-04-06
申请人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Chung-Hsun Lin , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/823437 , H01L22/34 , H01L27/0207 , H01L27/1203
摘要： Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a FET device is provided. The FET device includes a wafer; a plurality of active areas formed in the wafer; a plurality of gate stacks on the wafer, wherein at least one of the gate stacks is present over each of the active areas, and wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area; spacers on opposite sides of the gate stacks; and an angled implant in the source side of the given active area.
摘要翻译：提供了非对称FET器件及其制造方法，其采用可变间距栅极。一方面，提供一种FET器件。 FET器件包括晶片; 形成在晶片中的多个有源区; 晶片上的多个栅极堆叠，其中至少一个栅极堆叠存在于每个有源区域上，并且其中栅极堆叠具有不规则的栅极至栅极间隔，使得对于至少一个有源区域在给定有源区域的源极侧上的栅极至栅极间隔大于给定有源区域的漏极侧上的栅极至栅极间隔; 栅极堆叠的相对侧上的间隔物; 以及在给定活动区域的源侧的成角度的植入物。

9. 发明授权

US08536029B1 Nanowire FET and finFET 有权
标题翻译：纳米线FET和finFET
公开(公告)号：US08536029B1
公开(公告)日：2013-09-17
申请号：US13529334
申请日：2012-06-21
申请人： Josephine B. Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/845 , B82Y10/00 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： A method includes thinning a first region of an active layer, for form a stepped surface in the active layer defined by the first region and a second region of the active layer, depositing an planarizing layer on the active layer that defines a planar surface disposed on the active layer, etching to define nanowires and pads in the first region of the active layer, suspending the nanowires over the BOX layer, etching fins in the second region of the active layer forming a first gate stack that surrounds portion of each of the nanowires, forming a second gate stack covering a portion of the fins, and growing an epitaxial material wherein the epitaxial material defines source and drain regions of the nanowire FET and source and drain regions of the finFET.
摘要翻译：一种方法包括使有源层的第一区域变薄，以形成由有源层的第一区域和第二区域限定的有源层中的阶梯表面，在活性层上沉积限定平面的平坦化层，有源层，蚀刻以在有源层的第一区域中限定纳米线和焊盘，将纳米线悬挂在BOX层上，蚀刻有源层的第二区域中的鳍形成围绕每个纳米线的部分的第一栅极堆叠形成覆盖所述翅片的一部分的第二栅极堆叠，以及生长外延材料，其中所述外延材料限定所述纳米线FET的源极和漏极区域以及所述finFET的源极和漏极区域。

10. 发明授权

US08426917B2 Body-tied asymmetric P-type field effect transistor 有权
标题翻译：体系不对称P型场效应晶体管
公开(公告)号：US08426917B2
公开(公告)日：2013-04-23
申请号：US12683606
申请日：2010-01-07
申请人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
发明人： Jeffrey W. Sleight , Chung-Hsun Lin , Josephine B. Chang , Leland Chang
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78612 , H01L21/26586 , H01L29/1083 , H01L29/42384 , H01L29/66772
摘要： In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor.
摘要翻译：在本发明的一个示例性实施例中，非对称P型场效应晶体管包括：源极区，经由沟道耦合到漏极区; 覆盖所述通道的至少一部分的栅极结构; 至少部分地设置在所述通道中的卤素植入物，其中所述晕轮植入物设置成比所述漏极区域更靠近所述源极区域; 以及耦合到该通道的机身连接。在另一示例性实施例中，非对称P型场效应晶体管可用作对称P型场效应晶体管。

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