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1. 发明申请

US20060202941A1 SYSTEM AND METHOD FOR DETERMINING ILLUMINATION OF A PIXEL BY SHADOW PLANES 有权
标题翻译：用于通过阴影平面确定像素的照明的系统和方法
公开(公告)号：US20060202941A1
公开(公告)日：2006-09-14
申请号：US10906852
申请日：2005-03-09
申请人： Stephen Morein , Larry Seiler , Michael Doggett , Jocelyn Houle
发明人： Stephen Morein , Larry Seiler , Michael Doggett , Jocelyn Houle
IPC分类号： G09G3/36
CPC分类号： G06T15/50 , G06T15/005 , G06T15/60 , G06T15/80 , G06T2215/12
摘要： A graphics processing circuit includes a pixel shader operative to provide pixel color information in response to image data representing a scene to be rendered; a texture circuit, coupled to the pixel shader, operative to determine a luminance value to be applied to a pixel of interest based on the luminance values of the pixels that define a plane including the pixel of interest; and a render back end circuit, coupled to the texture circuit, operative to compute the luminance values from a shadow map that specifies the distance from the light source of the nearest object at a plurality of locations. A pixel illumination method includes receiving color information for a pixel to be rendered, defining a plane containing at least one pixel of interest, the plane including a plurality of planar values; comparing the plurality of planar values to a corresponding set of distance values; determining a luminance value for the at least one pixel of interest; and applying the luminance value to the at least one pixel of interest.
摘要翻译：图形处理电路包括像素着色器，用于响应于表示要渲染的场景的图像数据而提供像素颜色信息; 耦合到像素着色器的纹理电路，用于基于限定包括感兴趣像素的平面的像素的亮度值来确定要施加到感兴趣像素的亮度值; 以及耦合到纹理电路的渲染后端电路，用于从阴影图计算亮度值，所述阴影贴图指定在多个位置处距离最近物体的光源的距离。像素照明方法包括：接收要渲染的像素的颜色信息，定义包含至少一个感兴趣像素的平面，所述平面包括多个平面值; 将所述多个平面值与相应的一组距离值进行比较; 确定所述感兴趣的所述至少一个像素的亮度值; 以及将所述亮度值应用于所述至少一个感兴趣的像素。

2. 发明申请

US20050195187A1 Method and apparatus for hierarchical Z buffering and stenciling 有权
标题翻译：用于分级Z缓冲和模板的方法和装置
公开(公告)号：US20050195187A1
公开(公告)日：2005-09-08
申请号：US10790953
申请日：2004-03-02
申请人： Larry Seiler , Stephen Morein
发明人： Larry Seiler , Stephen Morein
IPC分类号： G06T15/40 , G06T1/20
CPC分类号： G06T15/405
摘要： A method and apparatus for hierarchical Z buffering stenciling includes comparing an input tile Z value range with a hierarchical Z value range and a stencil code. The method and apparatus also updates the hierarchical Z value range and stencil code in response the comparison and determines whether to render a plurality of pixels within the input tile based on the comparison of the input tile Z value range with the hierarchical Z value range and stencil code. In determining whether to render the tile, a stencil test and a hierarchical Z value test is performed. If one of the test fails, the tile is killed as it is determined that the pixels are not visible in the graphical output. If the stencil test passes and the hierarchical Z test passes, the pixels within the tile are rendered, as it is determined that the pixels may be visible.
摘要翻译：用于分层Z缓冲模板的方法和装置包括将输入图块Z值范围与分层Z值范围和模版代码进行比较。所述方法和装置还响应于比较而更新分层Z值范围和模板代码，并且基于输入瓦片Z值范围与分层Z值范围和模板的比较来确定是否在输入瓦片内呈现多个像素码。在确定是否渲染图块时，执行模板测试和分层Z值测试。如果其中一个测试失败，那么瓷砖将被杀死，因为确定像素在图形输出中不可见。如果模板测试通过并且层次化Z测试通过，则图块内的像素被渲染，因为确定像素可以是可见的。

3. 发明申请

US20050225558A1 Two level cache memory architecture 有权
标题翻译：两级缓存内存架构
公开(公告)号：US20050225558A1
公开(公告)日：2005-10-13
申请号：US10820580
申请日：2004-04-08
申请人： Stephen Morein , Michael Doggett
发明人： Stephen Morein , Michael Doggett
IPC分类号： G06F12/00 , G06F12/08 , G06F13/00 , G06T1/60 , G09G5/36
CPC分类号： G06F12/0897 , G06F3/14 , G06T1/60 , G09G2360/121 , G09G2360/125 , G09G2360/126
摘要： A memory architecture for use in a graphics processor including a main memory, a level one (L1) cache and a level two (L2) cache, coupled between the main memory and the L1 cache is disclosed. The L2 cache stores overlapping requests to the main memory before the requested information is stored in the L1 cache. In this manner, overlapping requests for previously stored information is retrieved from the faster L2 cache as opposed to the relatively slower main memory.
摘要翻译：公开了一种用于图形处理器的存储器架构，包括主存储器，第一级（L1）高速缓存和第二级（L2）高速缓存，耦合在主存储器和L1缓存之间。在所请求的信息存储在L1缓存中之前，L 2缓存将重叠的请求存储到主存储器。以这种方式，与较慢的主存储器相比，从较快的L 2高速缓存中检索先前存储的信息的重叠请求。

4. 发明申请

US20060033735A1 Method and apparatus for generating hierarchical depth culling characteristics 有权
公开(公告)号：US20060033735A1
公开(公告)日：2006-02-16
申请号：US10914949
申请日：2004-08-10
申请人： Larry Seiler , Laurent Lefebvre , Stephen Morein
发明人： Larry Seiler , Laurent Lefebvre , Stephen Morein
IPC分类号： G06T15/40
CPC分类号： G06T15/40
摘要： A method and apparatus for generating hierarchical depth culling characteristics includes determining a first minimum depth value and a first maximum depth value for a first graphical element. The graphical element may be a primitive. The first minimum depth value may be a minimum Z-plane depth of a pixel within the primitive and a first maximum depth value is a maximum Z-plane value for a pixel within the primitive. The method and apparatus further includes determining a second minimum depth value and a second maximum depth value for a second graphical element, which may be a tile. The method and apparatus further includes calculating an intersection depth range having an intersection minimum depth value and an intersection maximum depth value based on the intersection of the first minimum depth value and the first maximum depth value and the second minimum depth value and the second maximum depth value.

5. 发明授权

US08429356B2 Write data mask method and system 有权
标题翻译：写数据掩码的方法和系统
公开(公告)号：US08429356B2
公开(公告)日：2013-04-23
申请号：US11359809
申请日：2006-02-22
申请人： Joseph D. Macri , Stephen Morein , Ming-Ju E. Lee , Lin Chen
发明人： Joseph D. Macri , Stephen Morein , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F13/00
CPC分类号： G06F12/00 , G06F13/4234 , G06F13/4243 , G11C7/02 , G11C7/1006 , G11C7/1078 , G11C7/1096
摘要： A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.
摘要翻译：描述了用于执行字节写入的方法和系统，其中字节写入仅涉及仅写入多字节写入操作的特定字节。实施例包括指示在字节写入操作中要写入哪些字节的掩码数据。不使用专用的掩码引脚或专用掩码线。在一个实施例中，掩码数据在数据线上传输，并响应于write_mask命令存储。在一个实施例中，掩模数据作为写入命令的一部分被发送。

6. 发明授权

US07869525B2 Dynamic bus inversion method and system 有权
标题翻译：动态总线反演方法及系统
公开(公告)号：US07869525B2
公开(公告)日：2011-01-11
申请号：US11357291
申请日：2006-02-17
申请人： Joseph D. Macri , Stephen Morein , Ming-Ju E. Lee , Lin Chen
发明人： Joseph D. Macri , Stephen Morein , Ming-Ju E. Lee , Lin Chen
IPC分类号： H04B3/00
CPC分类号： H04L25/4915 , H03L7/07 , H03L7/0805 , H03L7/0814 , H04L7/0004 , H04L7/0008 , H04L7/0037 , H04L7/0337
摘要： A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.
摘要翻译：描述了动态总线反演（DBI）方法和系统。在各种实施例中，发射机通过多比特高速总线向接收机发送数据。在一个实施例中，发射机基于将要转换到新值的数据比特数来确定是否反转总线。如果确定总线被反相，则发送器对总线的共享线路上的DBI信号进行编码。在一个实施例中，共享线路在不同时间用于不同的目的，从而避免了对编码的DBI信号的专用线路或引脚的需要。接收器接收并解码DBI信号，作为响应，对接收到的数据进行适当的解码。

7. 发明申请

US20090125747A1 Asymmetrical IO Method and System 有权
标题翻译：非对称IO方法和系统
公开(公告)号：US20090125747A1
公开(公告)日：2009-05-14
申请号：US12356804
申请日：2009-01-21
申请人： Stephen Morein , Joseph Macri , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Stephen Morein , Joseph Macri , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F1/12
CPC分类号： H04L7/02 , H04L7/0025 , H04L7/0091
摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.
摘要翻译：描述了非对称IO方法和系统。在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。共享资源包括一个共享相位内插器。在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

8. 发明申请

US20070222787A1 MULTI-THREAD GRAPHICS PROCESSING SYSTEM 有权
标题翻译：多线程图形处理系统
公开(公告)号：US20070222787A1
公开(公告)日：2007-09-27
申请号：US11746453
申请日：2007-05-09
申请人： Laurent Lefebvre , Andrew Gruber , Stephen Morein
发明人： Laurent Lefebvre , Andrew Gruber , Stephen Morein
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06F9/3851 , G06T1/60 , G06T15/005 , G06T15/04 , G09G5/001 , G09G5/363
摘要： A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
摘要翻译：图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。提供耦合到所述至少一个存储器件的仲裁器，其基于所述多个像素命令线程和所述多个顶点命令线程的相对优先级从所述多个像素或顶点命令线程中选择命令线程。所选择的命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。

9. 发明授权

US06720964B1 Method and apparatus for processing portions of primitives that are being rendered 有权
标题翻译：用于处理正在渲染的图元的部分的方法和装置
公开(公告)号：US06720964B1
公开(公告)日：2004-04-13
申请号：US09457648
申请日：1999-12-09
申请人： Mark C. Fowler , Stephen Morein , Andi Skende , Kevin M. Olson
发明人： Mark C. Fowler , Stephen Morein , Andi Skende , Kevin M. Olson
IPC分类号： G06T1540
CPC分类号： G06T15/405
摘要： A method and apparatus for processing portions of primitives that are being rendered is presented. Primitives that are received are divided into portions that correspond to pixel blocks of the frame. The frame includes a plurality of pixel blocks where each of the pixel blocks includes a plurality of pixels that are included in the frame. Thus, the pixel blocks divide the frame into a number of smaller blocks. A representative Z value for each portion of the primitive is determined, and the representative Z value for the portion of the primitive is compared with a representative buffered Z, which may be the representative buffer Z value for the pixel block to which the portion corresponds. If the representative Z value for the portion compares favorably with the representative buffered Z value such that the portion is determined to lie completely behind the information currently stored for that pixel block, the portion is discarded. If the representative Z value for the portion compares with the representative buffer Z value in such a way that not all of the portion is ensured of being positioned behind currently buffered data for the pixel block, the portion of the primitive is processed further such that pixel fragments corresponding to the portion are generated and combined with the information currently stored for that pixel block. The representative buffered Z values for each of the pixel blocks may be derived based on a compression scheme applied to the Z values for each of the individual pixel blocks.
摘要翻译：呈现用于处理正在呈现的图元的部分的方法和装置。被接收的原语被分成对应于帧的像素块的部分。该帧包括多个像素块，其中每个像素块包括包括在帧中的多个像素。因此，像素块将帧划分成多个较小的块。确定基元的每个部分的代表性的Z值，并将原始部分的代表Z值与代表性的缓冲Z进行比较，代表性的缓冲Z可以是该部分对应的像素块的代表性缓冲器Z值。如果该部分的代表Z值与代表性缓冲的Z值相比有利地被确定为完全落在当前为该像素块存储的信息之后，则该部分被丢弃。如果该部分的代表Z值与代表性缓冲器Z值相比较，使得不保证所有部分都被定位在像素块的当前缓冲数据的后面，则进一步处理原语的该部分，使得像素产生与该部分相对应的片段，并与当前为该像素块存储的信息组合。可以基于应用于每个像素块的Z值的压缩方案来导出每个像素块的代表性缓冲的Z值。

10. 发明授权

US08661300B1 Error detection in high-speed asymmetric interfaces 有权
标题翻译：高速非对称接口中的错误检测
公开(公告)号：US08661300B1
公开(公告)日：2014-02-25
申请号：US13169977
申请日：2011-06-27
申请人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F11/00
CPC分类号： G06F11/10
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速非对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。所接收的签名与由第一组件存储的签名进行比较。两个签名对应于接口上的事务。基于比较，第一个组件确定事务是否成功，并根据需要引导第二个组件。

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