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    • 3. 发明申请
    • POWER CONNECTOR
    • 电源连接器
    • US20080064264A1
    • 2008-03-13
    • US11934532
    • 2007-11-02
    • Stephen ClarkJoseph ShueyJose OrtegaJohn Brown
    • Stephen ClarkJoseph ShueyJose OrtegaJohn Brown
    • H01R24/00
    • H01R13/11H01R12/7088H01R12/718H01R12/724H01R12/727H01R13/112
    • A pair of mating connectors includes a receptacle having an insulative housing and at least one conductive receptacle contact with a pair of spaced walls forming a plug contact receiving space. The plug connector has an insulative housing and at least one conductive contact having a pair of spaced walls which converge to form a projection engageable in the plug receiving space of the receptacle contact. In each case, the spaced walls are joined by a bridging structure that unites the walls. The plug and receptacle contacts are retained in the respective housings by engagement of opposed lateral edge portions of the contacts with the housings in a manner to enhance heat dissipation by convection by maintaining substantial portions of the contacts spaced from the housing walls and from each other. The bridging structure may include a retention element for engaging respective connector housings to retain the contact in the housings. The open structure of both the receptacle and plug contacts enhances heat dissipation and allows flexibility in achieving desired contact normal forces. The contact construction is especially useful for electronic power connectors.
    • 一对配合连接器包括具有绝缘外壳的插座和至少一个与一对间隔开的壁形成插头接触空间的导电插座触点。 插头连接器具有绝缘壳体和至少一个导电触头,该导电触头具有一对间隔开的壁,其汇合以形成可接合在插座触头的插头接收空间中的突起。 在每种情况下,间隔开的壁通过使壁连接的桥接结构连接。 插头和插座触头通过将触头的相对的侧边缘部分与壳体接合,以通过将接触件的大部分保持与壳体壁彼此隔开的方式通过对流来增强散热性而保持在相应的壳体中。 桥接结构可以包括用于接合相应的连接器壳体以将接触保持在壳体中的保持元件。 插座和插头触点的开放结构增强了散热性,并且允许实现期望的接触法向力的灵活性。 接触结构对于电子电源连接器特别有用。
    • 5. 发明授权
    • High CMOS open-drain output buffer
    • 高CMOS开漏输出缓冲器
    • US5028819A
    • 1991-07-02
    • US535403
    • 1990-06-08
    • Tom S. WeiElisabeth EkmanAndre WalkerStephen Clark
    • Tom S. WeiElisabeth EkmanAndre WalkerStephen Clark
    • H03K19/0185
    • H03K19/018571
    • A CMOS N-channel, open-drain, pull-down buffer circuit is capable of pulling down voltages on an external pad in excess of the breakdown voltage of the individual N-channel field effect transistors in the buffer circuit. The circuit may be fabricated as part of a CMOS interated circuit in an industrial standard 1.5 microns CMOS process. The higher voltage acceptance is effected by using two open-drain N-transistors in series such that the external voltage is divided among the two transistors. A parallel high voltage circuit to the external pad can be independently optimized to provide a lower impedance path and a higher endurance for electrostatic discharge. While the two-transistor voltage divider exposes one of the transistor' gate to ESD via another external terminal, enhanced ESD protection is effected by having a resistor in series between the gate and the external terminal.
    • CMOS N沟道,漏极开路下拉缓冲电路能够将外部焊盘上的电压拉低超过缓冲电路中各N沟道场效应晶体管的击穿电压。 该电路可以制造为工业标准1.5微米CMOS工艺中的CMOS电路的一部分。 通过使用两个串联的漏极开路N晶体管来实现较高的电压接受,使得外部电压在两个晶体管之间分配。 可以独立优化到外部焊盘的并联高压电路,以提供较低的阻抗路径和更高的静电放电耐久性。 当双晶体管分压器通过另一个外部端子将晶体管栅极之一暴露于ESD时,通过在栅极和外部端子之间串联一个电阻来实现增强的ESD保护。