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1. 发明授权

US08219960B1 Methods of implementing relocatable circuits in a programmable integrated circuit device 有权
标题翻译：在可编程集成电路器件中实现可重定位电路的方法
公开(公告)号：US08219960B1
公开(公告)日：2012-07-10
申请号：US12768933
申请日：2010-04-28
申请人： Stephen A. Neuendorffer , Parimal Patel
发明人： Stephen A. Neuendorffer , Parimal Patel
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for configuring programmable logic in an IC to implement instances of a relocatable circuit includes, for each instance, assigning a respective portion of an address space of a processor to the instance, configuring a respective interface circuit for translating the transactions accessing the respective portion of the address space into a fixed address space of the relocatable circuit, and selecting a respective region within an array of programmable logic and interconnect resources of the IC. The processor accesses the address space with read and write transactions issued on an interface bus. The relocatable circuit is independent of the address space assigned to the instances. Each region is configurable to implement an instance. The programmable logic and interconnect resources are configured to implement the instances and to couple each instance to the interface bus of the processor via the respective interface circuit, using a single copy of configuration data for the relocatable circuit.
摘要翻译：用于配置IC中的可编程逻辑以实现可重定位电路的实例的方法包括：针对每种情况，将处理器的地址空间的相应部分分配给所述实例，配置相应的接口电路以翻译访问相应部分的事务的地址空间转换成可重定位电路的固定地址空间，以及选择IC的可编程逻辑阵列和互连资源的阵列内的相应区域。处理器通过在接口总线上发出的读写事务访问地址空间。可重新定位的电路独立于分配给实例的地址空间。每个区域都可配置为实现一个实例。可编程逻辑和互连资源被配置为实现实例并且通过相应的接口电路将每个实例耦合到处理器的接口总线，使用用于可重定位电路的单个副本的配置数据。

2. 发明授权

US07765512B1 Relocatable circuit implemented in a programmable logic device 有权
标题翻译：可重定位电路在可编程逻辑器件中实现
公开(公告)号：US07765512B1
公开(公告)日：2010-07-27
申请号：US12054724
申请日：2008-03-25
申请人： Stephen A. Neuendorffer , Parimal Patel
发明人： Stephen A. Neuendorffer , Parimal Patel
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A circuit is implemented using a programmable logic device (PLD) that includes an array of programmable logic and routing resources. The circuit includes a processor, a configuration port, a relocatable circuit, and an interface circuit. The processor accesses an address space using read and write transactions issued on an interface bus. The programmable logic and interconnect resources are configurable via the configuration port. The relocatable circuit is implemented in a selected region within the array by configuring the programmable logic and interconnect resources in the selected region with configuration data via the configuration port. The interface circuit translates the transactions accessing a portion of the address space assigned to the relocatable circuit into a fixed address space of the relocatable circuit. The configuration data for implementing the relocatable circuit is independent of the portion of the address space assigned to the relocatable circuit.
摘要翻译：使用包括可编程逻辑和路由资源阵列的可编程逻辑器件（PLD）来实现电路。该电路包括处理器，配置端口，可重定位电路和接口电路。处理器使用在接口总线上发出的读写事务访问地址空间。可编程逻辑和互连资源可通过配置端口进行配置。可重新定位的电路通过配置可配置端口的配置数据配置可选择的区域中的可编程逻辑和互连资源，在阵列内的选定区域中实现。接口电路将访问分配给可重定位电路的地址空间的一部分的事务转换成可重定位电路的固定地址空间。用于实现可重定位电路的配置数据与分配给可重定位电路的地址空间的部分无关。

3. 发明授权

US07541833B1 Validating partial reconfiguration of an integrated circuit 有权
标题翻译：验证集成电路的部分重新配置
公开(公告)号：US07541833B1
公开(公告)日：2009-06-02
申请号：US11973781
申请日：2007-10-09
申请人： Stephen A. Neuendorffer , Brandon J. Blodget
发明人： Stephen A. Neuendorffer , Brandon J. Blodget
IPC分类号： H03K19/173
CPC分类号： H03K19/17756 , H03K19/17768
摘要： Approaches for validating a configuration bitstream used for partially reconfiguring an ingrated circuit such as a programmable logic device (PLD) are disclosed. In one approach, the integrated circuit is configured with a first configuration bitstream that includes first bit values that produce an implementation of a static part of a design on the integrated circuit. Any differences between a bit value in a second configuration bitstream and a corresponding bit value of the implementation of the static part of the design are determined. The second configuration bitstream includes second bit values that produce an implementation of a reconfigurable part of the design on the integrated circuit. A first signal state is output in response to determining that there are no differences, and a second signal state is output in response to determining that there are differences.
摘要翻译：公开了用于验证用于部分重新配置诸如可编程逻辑器件（PLD）之类的入口电路的配置比特流的方法。在一种方法中，集成电路配置有第一配置比特流，其包括产生集成电路上的设计的静态部分的实现的第一比特值。确定第二配置比特流中的比特值与设计的静态部分的实现的对应比特值之间的任何差异。第二配置比特流包括产生集成电路上的设计的可重新配置部分的实现的第二比特值。响应于确定没有差异而输出第一信号状态，并且响应于确定存在差异而输出第二信号状态。

4. 发明授权

US08020139B1 Method and apparatus for implementing a dataflow circuit model using application-specific memory implementations 有权
标题翻译：使用专用存储器实现来实现数据流电路模型的方法和装置
公开(公告)号：US08020139B1
公开(公告)日：2011-09-13
申请号：US12331212
申请日：2008-12-09
申请人： Stephen A. Neuendorffer , Ian D. Miller
发明人： Stephen A. Neuendorffer , Ian D. Miller
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/505
摘要： Method, apparatus, and computer readable medium for implementing a circuit model in an integrated circuit are described. In some examples, the circuit model includes a communication channel between actors. Data portions of at least one data object passed between the actors over the communication channel are identified. An implementation is generated for the circuit model in which data portions are assigned to either local queue storage of the communication channel or centralized shared storage of the communication channel based on levels of access thereof by the actors.
摘要翻译：描述了用于实现集成电路中的电路模型的方法，装置和计算机可读介质。在一些示例中，电路模型包括演员之间的通信信道。识别通过通信信道在演员之间传递的至少一个数据对象的数据部分。针对电路模型生成实现，其中数据部分被分配给通信信道的本地队列存储或通信信道的集中式共享存储器，其基于角色的访问级别。

5. 发明授权

US07834658B1 Interface generation for coupling to a high-bandwidth interface 有权
标题翻译：用于耦合到高带宽接口的接口生成
公开(公告)号：US07834658B1
公开(公告)日：2010-11-16
申请号：US11405895
申请日：2006-04-18
申请人： Stephen A. Neuendorffer , Paul M. Hartke , Paul R. Schumacher
发明人： Stephen A. Neuendorffer , Paul M. Hartke , Paul R. Schumacher
IPC分类号： H03K19/173
CPC分类号： G06F13/4009 , G06F2213/0038
摘要： Method and apparatus for communication of data is described. More particularly, generation of an interface for coupling to an auxiliary processor unit for communication of data in an integrated circuit is described. Programmable logic is programmed to provide a hardware interface for communicating the data between memory and a user-defined circuit. The data is communicated at least in part via an auxiliary processor unit coupled to the hardware interface. The programming includes configuring the programmable logic to use the auxiliary processor unit to respond to coded instructions executed by a central processing unit through the provided hardware interface.
摘要翻译：描述用于数据通信的方法和装置。更具体地，描述了用于耦合到用于在集成电路中的数据通信的辅助处理器单元的接口的生成。可编程逻辑被编程为提供用于在存储器和用户定义的电路之间传送数据的硬件接口。至少部分地经由耦合到硬件接口的辅助处理器单元传送数据。编程包括配置可编程逻辑以使用辅助处理器单元通过所提供的硬件接口来响应由中央处理单元执行的编码指令。

6. 发明授权

US08359448B1 Specific memory controller implemented using reconfiguration 有权
标题翻译：使用重新配置实现的特定内存控制器
公开(公告)号：US08359448B1
公开(公告)日：2013-01-22
申请号：US12505380
申请日：2009-07-17
申请人： Stephen A. Neuendorffer
发明人： Stephen A. Neuendorffer
IPC分类号： G06F12/02
CPC分类号： G06F17/5054
摘要： A circuit controls a memory arrangement and includes an array of programmable resources and interconnect resources, a reconfiguration port, and a processor. The programmable resources and interconnect resources in the array are initially configured with a reference configuration data-set. The reference configuration data-set configures the programmable resources and interconnect resources to implement a general memory controller. The processor obtains a characteristic of the memory arrangement and selects a particular partial reconfiguration data-set based on the characteristic of the memory arrangement. The processor reconfigures the programmable resources and interconnect resources in the array via the reconfiguration port. The processor reconfigures the programmable resources and interconnect resources with the particular partial reconfiguration data-set. The particular partial reconfiguration data-set partially reconfigures the programmable resources and interconnect resources to implement a portion of a specific memory controller that differs from the general memory controller.
摘要翻译：电路控制存储器布置并且包括可编程资源和互连资源的阵列，重新配置端口和处理器。阵列中的可编程资源和互连资源最初配置有参考配置数据集。参考配置数据集配置可编程资源和互连资源以实现一般的存储器控制器。处理器获得存储器装置的特性，并且基于存储器装置的特性来选择特定的部分重配置数据集。处理器通过重新配置端口重新配置可编程资源并互连阵列中的资源。处理器重新配置可编程资源并且利用特定的部分重配置数据集来互连资源。特定的部分重配置数据集部分地重新配置可编程资源并互连资源以实现与一般存储器控制器不同的特定存储器控制器的一部分。

7. 发明授权

US08116334B1 Dataflow FIFO communication buffer using highly-multiported memories 有权
标题翻译：数据流FIFO通信缓冲区使用高度多端口的存储器
公开(公告)号：US08116334B1
公开(公告)日：2012-02-14
申请号：US12962438
申请日：2010-12-07
申请人： Stephen A. Neuendorffer
发明人： Stephen A. Neuendorffer
IPC分类号： H04L12/28 , H04L12/56 , H04L1/00 , H04L12/26
CPC分类号： G06F17/5054
摘要： A First In First Out (FIFO) communication buffer for receiving data from a source and distributing the data to a first sink and a second sink is disclosed. The FIFO communication buffer includes a FIFO memory and a FIFO control circuit. The FIFO memory includes a first data port, a second data port, and a third data port. The FIFO control circuit provides the first address, the second address and the third address. The FIFO control circuit increments the first address toward the second address and the third address when valid data is received, and increments the second address and the third address when data is read out.
摘要翻译：公开了一种用于从源接收数据并将数据分发到第一宿和第二宿的先进先出（FIFO）通信缓冲器。 FIFO通信缓冲器包括FIFO存储器和FIFO控制电路。 FIFO存储器包括第一数据端口，第二数据端口和第三数据端口。 FIFO控制电路提供第一地址，第二地址和第三地址。当接收到有效数据时，FIFO控制电路将第一地址递增到第二地址和第三地址，并且在读出数据时递增第二地址和第三地址。

8. 发明授权

US07895026B1 Multi-rate simulation scheduler for synchronous digital circuits in a high level modeling system 有权
标题翻译：在高级建模系统中同步数字电路的多速率模拟调度器
公开(公告)号：US07895026B1
公开(公告)日：2011-02-22
申请号：US11893570
申请日：2007-08-16
申请人： Sean A. Kelly , Stephen A. Neuendorffer , Haibing Ma
发明人： Sean A. Kelly , Stephen A. Neuendorffer , Haibing Ma
IPC分类号： G06F17/50 , G06F9/455 , G06F1/00
CPC分类号： G06F17/5027
摘要： A computer-implemented method of scheduling a multi-rate, synchronous circuit design for simulation within a high-level modeling system. The method can include determining a component clocking rate for each of a plurality of synchronous components of the circuit design and classifying each of the plurality of synchronous components into a plurality of schedules according to component clocking rate. For each clock cycle during simulation, the method can include selecting one of the plurality of schedules and executing each synchronous component of the selected schedule. A value determined through execution of a synchronous component of the circuit design can be output.
摘要翻译：一种计算机实现的方法，用于在高级建模系统中调度用于模拟的多速率同步电路设计。该方法可以包括确定电路设计的多个同步分量中的每一个的组件时钟速率，并根据组件时钟速率将多个同步组件中的每一个分类为多个调度。对于仿真期间的每个时钟周期，该方法可以包括选择多个调度中的一个并执行所选择的调度的每个同步分量。可以输出通过执行电路设计的同步分量确定的值。

9. 发明授权

US07869452B1 Dataflow FIFO communication buffer using highly-multiported memories 有权
标题翻译：数据流FIFO通信缓冲区使用高度多端口的存储器
公开(公告)号：US07869452B1
公开(公告)日：2011-01-11
申请号：US11880160
申请日：2007-07-19
申请人： Stephen A. Neuendorffer
发明人： Stephen A. Neuendorffer
IPC分类号： H04L12/28 , H04L12/56 , H04L1/00 , H04L12/26
CPC分类号： G06F17/5054
摘要： A FIFO communication system is provided using a FIFO and connection circuit to transmit data from a single source to multiple sinks. The connection circuit operates to enable simultaneous reads by the multiple sinks with a single output port FIFO. Multiple FIFOs can likewise be used to distribute data from a single source to multiple sinks without requiring a simultaneous read by both sinks. Similarly, a multiple output port FIFO can be used to supply multiple sinks without requiring simultaneous reads and without requiring additional memory use.
摘要翻译：使用FIFO和连接电路提供FIFO通信系统，以将数据从单个源传输到多个汇。连接电路操作以使得能够通过单个输出端口FIFO同时读取多个接收器。同样可以使用多个FIFO来将数据从单个源分配到多个汇，而不需要两个汇的同时读取。类似地，可以使用多输出端口FIFO来提供多个汇，而不需要同时读取，而不需要额外的存储器使用。

10. 发明授权

US08245243B1 Transforming device drivers to improve efficiency 有权
标题翻译：转换设备驱动程序以提高效率
公开(公告)号：US08245243B1
公开(公告)日：2012-08-14
申请号：US12498192
申请日：2009-07-06
申请人： Stephen A. Neuendorffer
发明人： Stephen A. Neuendorffer
IPC分类号： G06F13/00 , G06F13/10
CPC分类号： G06F13/102
摘要： Efficiency is improved for device drivers. A first library is input that includes a first version of the device drivers. First metadata is input that specifies the devices of the computing arrangement and associates each device with the first version of a corresponding device driver. The first version of the corresponding device driver for each device is transformed into a second version of the corresponding device driver. The first version of the corresponding device driver indirectly accesses the device and the second version of the corresponding device driver directly accesses the device. A second library is output including the second version of the corresponding device driver for each device.
摘要翻译：设备驱动程序的效率得到改善。第一个库是包含设备驱动程序的第一个版本的输入。第一元数据是指定计算装置的设备并将每个设备与对应的设备驱动程序的第一版本相关联的输入。每个设备的相应设备驱动程序的第一个版本被转换成相应设备驱动程序的第二个版本。相应设备驱动程序的第一个版本间接访问设备，相应的设备驱动程序的第二个版本直接访问设备。输出第二个库，包括每个设备的相应设备驱动程序的第二个版本。

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