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1. 发明授权

US06875699B1 Method for patterning multilevel interconnects 有权
标题翻译：图形化多层互连的方法
公开(公告)号：US06875699B1
公开(公告)日：2005-04-05
申请号：US10138041
申请日：2002-05-01
申请人： Stephan Lassig , S. M. Reza Sadjadi , Vinay Pohray , Si Yi Li , Thomas W. Mountsier , Chiu Chi
发明人： Stephan Lassig , S. M. Reza Sadjadi , Vinay Pohray , Si Yi Li , Thomas W. Mountsier , Chiu Chi
IPC分类号： G03F7/09 , H01L21/311 , H01L21/312 , H01L21/316 , H01L21/768 , H01L21/302
CPC分类号： H01L21/02063 , G03F7/091 , H01L21/31116 , H01L21/31138 , H01L21/312 , H01L21/3124 , H01L21/3127 , H01L21/31629 , H01L21/31695 , H01L21/76808 , H01L21/76829
摘要： A method of forming a damascene structure above a substrate is provided. A low-k dielectric layer is formed over the substrate, wherein the low-k dielectric layer does not have a trench stop layer. A plurality of vias are etched through the low-k dielectric layer. Via plugs are formed in the plurality of vias. A plurality of trenches are etched into the low-k dielectric layer, wherein the etching with sufficiently high via plugs minimizes facet formation at the tops of vias exposed to the etch and wherein the trench etch process removes fences caused by the via plugs. The via plugs are stripped.
摘要翻译：提供了一种在衬底上形成镶嵌结构的方法。低k电介质层形成在衬底上，其中低k电介质层不具有沟槽停止层。通过低k电介质层蚀刻多个通孔。通过插塞形成在多个通孔中。多个沟槽被蚀刻到低k电介质层中，其中具有足够高的通孔插塞的蚀刻最小化暴露于蚀刻的通孔顶部的小面形成，并且其中沟槽蚀刻工艺移除由通孔插塞引起的栅栏。通孔塞被剥去。

2. 发明授权

US06794293B2 Trench etch process for low-k dielectrics 有权
标题翻译：低k电介质的沟槽蚀刻工艺
公开(公告)号：US06794293B2
公开(公告)日：2004-09-21
申请号：US09972765
申请日：2001-10-05
申请人： SiYi Li , S. M. Reza Sadjadi , David R. Pirkle , Steve Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
发明人： SiYi Li , S. M. Reza Sadjadi , David R. Pirkle , Steve Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
IPC分类号： H01L21302
CPC分类号： H01L21/31116 , H01L21/02126 , H01L21/31138 , H01L21/312 , H01L21/3124 , H01L21/3127 , H01L21/31629 , H01L21/31695 , H01L21/76804 , H01L21/76808
摘要： The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.
摘要翻译：本发明是一种在电介质层内形成沟槽的方法，包括：首先蚀刻电介质层内的通孔。在蚀刻通孔之后，使用有机插塞来填充通孔的一部分。在从通孔蚀刻所需量的有机插塞之后，用第一气体混合物蚀刻沟槽至第一深度，并且使用第二气体混合物来进一步将沟槽蚀刻到最终期望的沟槽深度。优选地，该方法用于不具有中间蚀刻停止层的低k电介质。另外，优选地，第一气体混合物是聚合气体混合物，第二气体混合物是非聚合气体混合物。作为使用该方法的结果，产生用于低k电介质的互连结构，而不具有中间蚀刻停止层，该中间蚀刻停止层具有沟槽边缘，其基本上正交，并且具有基本正交的通孔边缘的通孔。

3. 发明授权

US06909195B2 Trench etch process for low-k dielectrics 有权
公开(公告)号：US06909195B2
公开(公告)日：2005-06-21
申请号：US10826211
申请日：2004-04-16
申请人： SiYi Li , S. M. Reza Sadjadi , David R. Pirkle , Steve Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
发明人： SiYi Li , S. M. Reza Sadjadi , David R. Pirkle , Steve Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
IPC分类号： H01L21/311 , H01L21/312 , H01L21/316 , H01L21/768 , H01L23/48
CPC分类号： H01L21/31116 , H01L21/02126 , H01L21/31138 , H01L21/312 , H01L21/3124 , H01L21/3127 , H01L21/31629 , H01L21/31695 , H01L21/76804 , H01L21/76808
摘要： The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

4. 发明授权

US07311852B2 Method of plasma etching low-k dielectric materials 有权
标题翻译：等离子体蚀刻低k电介质材料的方法
公开(公告)号：US07311852B2
公开(公告)日：2007-12-25
申请号：US09820695
申请日：2001-03-30
申请人： Si Yi Li , Helen H. Zhu , S. M. Reza Sadjadi , James V. Tietz , Bryan A. Helmer
发明人： Si Yi Li , Helen H. Zhu , S. M. Reza Sadjadi , James V. Tietz , Bryan A. Helmer
IPC分类号： H01L21/3065
CPC分类号： H01L21/7681 , H01L21/31116 , H01L21/31138 , H01L21/76807
摘要： A semiconductor manufacturing process wherein a low-k dielectric layer is plasma etched with selectivity to an overlying mask layer. The etchant gas can be oxygen-free and include a fluorocarbon reactant, a nitrogen reactant and an optional carrier gas, the fluorocarbon reactant and nitrogen reactant being supplied to a chamber of a plasma etch reactor at flow rates such that the fluorocarbon reactant flow rate is less than the nitrogen reactant flow rate. The etch rate of the low-k dielectric layer can be at least 5 times higher than that of a silicon dioxide, silicon nitride, silicon oxynitride or silicon carbide mask layer. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.
摘要翻译：一种半导体制造工艺，其中低k电介质层被等离子体蚀刻，对上覆掩模层具有选择性。蚀刻剂气体可以是无氧的并且包括氟碳反应物，氮反应物和任选的载气，所述碳氟反应物和氮反应物以流速供给到等离子体蚀刻反应器的室，使得碳氟化合物反应物流速为小于氮气反应物流量。低k电介质层的蚀刻速率可以比二氧化硅，氮化硅，氮氧化硅或碳化硅掩模层的蚀刻速率高至少5倍。该方法对于在形成结构如镶嵌结构中蚀刻0.25微米和较小的接触或通孔开口是有用的。

5. 发明授权

US07166535B2 Plasma etching of silicon carbide 失效
标题翻译：碳化硅等离子体蚀刻
公开(公告)号：US07166535B2
公开(公告)日：2007-01-23
申请号：US10430013
申请日：2003-05-06
申请人： Si Yi Li , S. M. Reza Sadjadi , James V. Tietz
发明人： Si Yi Li , S. M. Reza Sadjadi , James V. Tietz
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/3065 , H01L21/31116 , H01L21/32137
摘要： A process for plasma etching silicon carbide with selectivity to an overlying and/or underlying dielectric layer of material. The dielectric material can comprise silicon dioxide, silicon oxynitride, silicon nitride or various low-k dielectric materials including organic low-k materials. The etching gas includes a chlorine containing gas such as Cl2, an oxygen containing gas such as O2, and a carrier gas such as Ar. In order to achieve a desired selectivity to such dielectric materials, the plasma etch gas chemistry is selected to achieve a desired etch rate of the silicon carbide while etching the dielectric material at a slower rate. The process can be used to selectively etch a hydrogenated silicon carbide etch stop layer or silicon carbide substrate.
摘要翻译：用于等离子体蚀刻碳化硅的方法，其具有对材料的上覆和/或下层介电层的选择性。介电材料可以包括二氧化硅，氮氧化硅，氮化硅或包括有机低k材料的各种低k电介质材料。蚀刻气体包括诸如Cl 2的含氯气体，诸如O 2的含氧气体和诸如Ar的载气。为了实现对这种介电材料的期望的选择性，选择等离子体蚀刻气体化学物质以在较慢的速率蚀刻电介质材料时实现所需的碳化硅蚀刻速率。该方法可用于选择性蚀刻氢化碳化硅蚀刻停止层或碳化硅衬底。

6. 发明授权

US06919278B2 Method for etching silicon carbide 有权
标题翻译：腐蚀碳化硅的方法
公开(公告)号：US06919278B2
公开(公告)日：2005-07-19
申请号：US10199190
申请日：2002-07-19
申请人： Sean S. Kang , Si Yi Li , S. M. Reza Sadjadi
发明人： Sean S. Kang , Si Yi Li , S. M. Reza Sadjadi
IPC分类号： H01J37/00 , H01L21/04 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/3213 , H01L21/461 , H01L21/768
CPC分类号： H01L21/3065 , H01L21/31116 , H01L21/32137
摘要： A system and method for achieving a silicon carbide to low-k dielectric etch selectivity ratio of greater than 1:1 using a chlorine containing gas and either hydrogen (H2) gas or nitrogen (N2) gas is described. The method is applied to a semiconductor substrate having a low-k dielectric layer and a silicon carbide layer. The chlorine containing gas is a gas mixture that includes either HCl, BCl3, Cl2, or any combination thereof. In one embodiment, the method provides for supplying an etchant gas comprising a chlorine containing gas and a hydrogen (H2) gas. The etchant gas is then energized to generate a plasma which then etches openings in the silicon carbide at a faster etch rate than the low-k dielectric etch rate. In an alternative embodiment, the etchant gas mixture comprises a chlorine containing gas and a nitrogen (N2) gas.
摘要翻译：一种用于使用含氯气体和氢气（H 2/2）气体或氮气（N 2）的气体来实现碳化硅至低k电介质蚀刻选择比大于1:1的系统和方法， 2气体）。该方法应用于具有低k电介质层和碳化硅层的半导体衬底。含氯气体是包含HCl，BCl 3，Cl 2 H 2或其任何组合的气体混合物。在一个实施方案中，该方法提供了供应包含含氯气体和氢气（H 2 H 2）气体的蚀刻剂气体。然后将蚀刻剂气体通电以产生等离子体，然后等离子体以比低k电介质蚀刻速率更快的蚀刻速率蚀刻碳化硅中的开口。在替代实施例中，蚀刻剂气体混合物包括含氯气体和氮气（N 2/2）气体。

7. 发明授权

US06670278B2 Method of plasma etching of silicon carbide 有权
公开(公告)号：US06670278B2
公开(公告)日：2003-12-30
申请号：US09820726
申请日：2001-03-30
申请人： Si Yi Li , Helen H. Zhu , S. M. Reza Sadjadi , David R. Pirkle , James Bowers , Michael Goss
发明人： Si Yi Li , Helen H. Zhu , S. M. Reza Sadjadi , David R. Pirkle , James Bowers , Michael Goss
IPC分类号： H01L21302
CPC分类号： H01L21/7681 , H01L21/31116 , H01L21/76807
摘要： The invention provides a process for plasma etching silicon carbide with selectivity to an overlapping and/or underlying dielectric layer of material. The etching gas includes a hydrogen-containing fluorocarbon gas such as CH3F, an oxygen-containing gas such as O2 and an optional carrier gas such as Ar. The dielectric material can comprise silicon dioxide, silicon nitride, silicon oxynitride or various low-k dielectric materials including organic low-k materials. In order to achieve a desired selectivity to such dielectric materials, the plasma etch gas chemistry is selected to achieve a desired etch rate of the silicon carbide while etching the dielectric material at a slower rate. The process can be used to selectively etch a hydrogenated silicon carbide etch stop layer or silicon carbide substrates.

8. 发明授权

US08268118B2 Critical dimension reduction and roughness control 有权
标题翻译：关键尺寸减小和粗糙度控制
公开(公告)号：US08268118B2
公开(公告)日：2012-09-18
申请号：US12711420
申请日：2010-02-24
申请人： Sangheon Lee , Dae-Han Choi , Jisoo Kim , Peter Cirigliano , Zhisong Huang , Robert Charatan , S. M. Reza Sadjadi
发明人： Sangheon Lee , Dae-Han Choi , Jisoo Kim , Peter Cirigliano , Zhisong Huang , Robert Charatan , S. M. Reza Sadjadi
IPC分类号： H01L21/3065
CPC分类号： C23F4/00 , H01L21/31116 , H01L21/31144 , H01L21/76816 , Y10S438/947
摘要： A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.
摘要翻译：提供了一种在蚀刻层中形成特征的方法。在蚀刻层上形成光致抗蚀剂层。图案化光致抗蚀剂层以形成具有光致抗蚀剂侧壁的光致抗蚀剂特征。在光致抗蚀剂层和光致抗蚀剂特征的底部上形成控制层。在光致抗蚀剂特征和控制层的侧壁上沉积保形层以减少光刻胶特征的临界尺寸。控制层的开口打开，控制层突破性化学。特征被蚀刻到蚀刻层中，其蚀刻化学性质不同于控制层突破性化学，其中控制层比蚀刻化学性质比共形层更耐蚀刻蚀刻。

9. 发明授权

US08172980B2 Device with self aligned gaps for capacitance reduction 有权
标题翻译：具有自对准间隙的器件，用于降低电容
公开(公告)号：US08172980B2
公开(公告)日：2012-05-08
申请号：US12202043
申请日：2008-08-29
申请人： S. M. Reza Sadjadi , Zhi-Song Huang
发明人： S. M. Reza Sadjadi , Zhi-Song Huang
IPC分类号： C23F1/00 , H01L21/306 , C23C16/00
CPC分类号： H01L21/7682 , H01J37/32623 , H01J37/32633 , H01J37/32642 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, where spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer. Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. Gaps are etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
摘要翻译：提供了用于降低半导体器件布线之间的电容的方法。在电介质层上形成牺牲层。多个特征被蚀刻到牺牲层和电介质层中。功能填充填充材料。去除牺牲层，使得填充材料的部分保持暴露在电介质层的表面之上，其中空间位于填充材料的暴露部分之间，其中空间在先前被牺牲层占据的区域中。填充材料部分之间的间隙的宽度随收缩侧壁沉积而收缩。通过收缩侧壁沉积将间隙蚀刻到介电层中。去除填充材料和收缩侧壁沉积。

10. 发明授权

US07977242B2 Double mask self-aligned double patterning technology (SADPT) process 有权
标题翻译：双面膜自对准双图案技术（SADPT）工艺
公开(公告)号：US07977242B2
公开(公告)日：2011-07-12
申请号：US12366113
申请日：2009-02-05
申请人： S. M. Reza Sadjadi , Lumin Li , Andrew R. Romano
发明人： S. M. Reza Sadjadi , Lumin Li , Andrew R. Romano
IPC分类号： H01L21/461 , H01L21/311
CPC分类号： H01L21/0337
摘要： A method for providing features in an etch layer is provided by forming an organic mask layer over the inorganic mask layer, forming a silicon-containing mask layer over the organic mask layer, forming a patterned mask layer over the silicon-containing mask layer, etching the silicon-containing mask layer through the patterned mask, depositing a polymer over the etched silicon-containing mask layer, depositing a silicon-containing film over the polymer, planarizing the silicon-containing film, selectively removing the polymer leaving the silicon-containing film, etching the organic layer, and etching the inorganic layer.
摘要翻译：通过在无机掩模层上形成有机掩模层，在有机掩模层上形成含硅掩模层，在含硅掩模层上形成图案化掩模层，蚀刻，提供蚀刻层中提供特征的方法通过图案化掩模的含硅掩模层，在蚀刻的含硅掩模层上沉积聚合物，在聚合物上沉积含硅膜，平坦化含硅膜，选择性地除去离开含硅膜的聚合物蚀刻有机层，并蚀刻无机层。

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