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1. 发明申请

US20140189250A1 Store Forwarding for Data Caches 有权
标题翻译：存储转发数据高速缓存
公开(公告)号：US20140189250A1
公开(公告)日：2014-07-03
申请号：US13729945
申请日：2012-12-28
申请人： Steffen Kosinski , Fernando Latorre , Niranjan Cooray , Stanislav Shwartsman , Ethan Kalifon , Varun Mohandru , Pedro Lopez , Tom Aviram-Rosenfeld , Jaroslav Topp , Li-Gao Zei
发明人： Steffen Kosinski , Fernando Latorre , Niranjan Cooray , Stanislav Shwartsman , Ethan Kalifon , Varun Mohandru , Pedro Lopez , Tom Aviram-Rosenfeld , Jaroslav Topp , Li-Gao Zei
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0855 , G06F12/0866
摘要： A bit or other vector may be used to identify whether an address range entered into an intermediate buffer corresponds to most recently updated data associated with the address range. A bit or other vector may also be used to identify whether an address range entered into an intermediate buffer overlaps with an address range of data that is to be loaded. A processing device may then determine whether to obtain data that is to be loaded entirely from a cache, entirely from an intermediate buffer which temporarily buffers data destined for a cache until the cache is ready to accept the data, or from both the cache and the intermediate buffer depending on the particular vector settings. Systems, devices, methods, and computer readable media are provided.
摘要翻译：可以使用位或其他向量来识别输入中间缓冲器的地址范围是否对应于与地址范围相关联的最近更新的数据。还可以使用位或其他向量来识别输入中间缓冲器的地址范围是否与要加载的数据的地址范围重叠。然后，处理设备可以完全从中间缓冲区获得要从缓存中完全加载的数据，该中间缓冲器临时缓冲目的地为高速缓存的数据，直到高速缓存准备好接受数据，或者从高速缓存和中间缓冲区取决于特定的向量设置。提供了系统，设备，方法和计算机可读介质。

2. 发明申请

US20140181388A1 Method And Apparatus To Implement Lazy Flush In A Virtually Tagged Cache Memory 有权
标题翻译：在几乎标记的高速缓冲存储器中实现懒惰冲洗的方法和装置
公开(公告)号：US20140181388A1
公开(公告)日：2014-06-26
申请号：US13724848
申请日：2012-12-21
申请人： Varun K. Mohandru , Fernando Latorre , NIRANJAN L. COORAY , Pedro Lopez , NAVEEN NEELAKANTAM , LI-GAO ZEI , RAMI MAY , JAROSLAW TOPP , THOMAS GAERTNER
发明人： Varun K. Mohandru , Fernando Latorre , NIRANJAN L. COORAY , Pedro Lopez , NAVEEN NEELAKANTAM , LI-GAO ZEI , RAMI MAY , JAROSLAW TOPP , THOMAS GAERTNER
IPC分类号： G11C7/10 , G06F12/08
CPC分类号： G11C7/1072 , G06F12/0804 , G06F12/0891 , G06F12/1036
摘要： A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed.
摘要翻译：处理器包括处理器核心，其包括执行指令的执行单元和高速缓冲存储器。高速缓冲存储器包括控制器，以响应于惰性冲洗指令来更新多个陈旧指示器中的每一个。每个陈旧的指示符与相应的数据相关联，每个更新的陈旧指示符指示相应的数据是否过时。高速缓冲存储器还包括多条高速缓存行。每个高速缓存行将存储对应的数据和前景标签，其包括与对应的数据相关联的相应的虚拟地址，并且其包括相关联的陈旧指示符。其他实施例被描述为所要求保护的。

3. 发明申请

US20140281351A1 STRIDE-BASED TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHING WITH ADAPTIVE OFFSET 有权
标题翻译：基于STRIDE的翻译LOOKASIDE BUFFER（TLB）使用自适应偏移
公开(公告)号：US20140281351A1
公开(公告)日：2014-09-18
申请号：US13799582
申请日：2013-03-13
申请人： Jaroslaw Topp , Pedro Lopez , Fernando Latorre , Demos Pavlou , Thang Vu
发明人： Jaroslaw Topp , Pedro Lopez , Fernando Latorre , Demos Pavlou , Thang Vu
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/0862 , G06F2212/602 , G06F2212/6026 , G06F2212/654
摘要： A processing device implementing stride-based translation lookaside buffer (TLB) prefetching with adaptive offset is disclosed. A processing device of the disclosure includes a data prefetcher to generate a data prefetch address based on a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, and a TLB prefetch address computation component to generate a TLB prefetch address based on the linear address, the stride, the prefetch distance, or an adaptive offset. The processing device also includes a cross page detection component to determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and cause a TLB prefetch request to be written to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) based on the data prefetch address or the TLB prefetch address.
摘要翻译：公开了一种利用自适应偏移实现基于步幅翻译后备缓冲器（TLB）预取的处理装置。本公开的处理设备包括数据预取器，用于基于线性地址，步幅或预取距离生成数据预取地址，与数据预取请求相关联的数据预取地址以及TLB预取地址计算组件以产生基于线性地址，步幅，预取距离或自适应偏移的TLB预取地址。该处理设备还包括一个跨页检测组件，用于确定数据预取地址或TLB预取地址与与线性地址相关联的页边界交叉，并且使TLB预取请求被写入TLB请求队列，TLB预取基于数据预取地址或TLB预取地址来请求翻译线性页码（LPN）的地址。

4. 发明申请

US20140095849A1 INSTRUCTION AND LOGIC FOR OPTIMIZATION LEVEL AWARE BRANCH PREDICTION 审中-公开
标题翻译：指导和逻辑优化水平分支预测
公开(公告)号：US20140095849A1
公开(公告)日：2014-04-03
申请号：US13631402
申请日：2012-09-28
申请人： Polychronis Xekalakis , Pedro Marcuello , Alejandro Vicente Martinez , Christos E. Kotselidis , Grigorios Magklis , Fernando Latorre , Raul Martinez , Josep M. Codina , Enric Gibert Codina , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Pedro Lopez , Marc Lupon , Carlos Madriles , Daniel Ortega , Demos Pavlou , Kyriakos A. Stavrou , Georgios Tournavitis
发明人： Polychronis Xekalakis , Pedro Marcuello , Alejandro Vicente Martinez , Christos E. Kotselidis , Grigorios Magklis , Fernando Latorre , Raul Martinez , Josep M. Codina , Enric Gibert Codina , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Pedro Lopez , Marc Lupon , Carlos Madriles , Daniel Ortega , Demos Pavlou , Kyriakos A. Stavrou , Georgios Tournavitis
IPC分类号： G06F9/38
CPC分类号： G06F9/38 , G06F9/30036 , G06F9/3848 , G06F9/3877 , G06F9/3887 , G06F9/3889
摘要： A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.
摘要翻译：描述了用于优化级感知分支预测的计算机可读存储介质，方法和系统。齿轮级别被分配给已优化的一组应用指令。齿轮级也存储在处理器的分支预测单元的寄存器中。然后由处理器基于齿轮级执行分支预测。

5. 发明申请

US20130332705A1 PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTWARE AT CODE REGION GRANULARITY 有权
标题翻译：根据代码区域格式的软件执行情况分析异常事件
公开(公告)号：US20130332705A1
公开(公告)日：2013-12-12
申请号：US13993054
申请日：2011-12-29
申请人： Raul Martinez , Enric Gibert Codina , Pedro Lopez , Marti Torrents Lapuerta , Polychronis Xekalakis , Georgios Tournavitis , Kyriakos A. Stavrou , Demos Pavlou , Daniel Ortega , Alejandro Martinez Vicente , Pedro Marcuello , Grigorios Magklis , Josep M. Codina , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Christos Kotselidis , Fernando Latorre , Marc Lupon , Carlos Madriles
发明人： Raul Martinez , Enric Gibert Codina , Pedro Lopez , Marti Torrents Lapuerta , Polychronis Xekalakis , Georgios Tournavitis , Kyriakos A. Stavrou , Demos Pavlou , Daniel Ortega , Alejandro Martinez Vicente , Pedro Marcuello , Grigorios Magklis , Josep M. Codina , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Christos Kotselidis , Fernando Latorre , Marc Lupon , Carlos Madriles
IPC分类号： G06F9/30
CPC分类号： G06F11/3037 , G06F11/3409 , G06F11/3466 , G06F12/0862 , G06F2201/86 , G06F2201/865 , G06F2201/88 , G06F2201/885
摘要： A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.
摘要翻译：硬件和软件的组合以代码区域粒度收集用于异步事件的简档数据。示例性实施例涉及收集在本质上是异步的预取事件的度量。使用几种替代技术之一来标识属于代码区域的指令，使得为指令设置配置文件位作为标记。预取数据块的每一行都被类似地标记。然后识别与正在收集并且由代码区域内的指令产生的简档数据相对应的事件。每次识别出不同类型的事件之一时，相应的计数器将被递增。在代码区域中执行指令之后，收集在计数器中累积的简档数据，并且重置计数器以与新的代码区域一起使用。

6. 发明申请

US20100269102A1 SYSTEMS, METHODS, AND APPARATUSES TO DECOMPOSE A SEQUENTIAL PROGRAM INTO MULTIPLE THREADS, EXECUTE SAID THREADS, AND RECONSTRUCT THE SEQUENTIAL EXECUTION 有权
标题翻译：将顺序程序分解成多个线程的系统，方法和装置，执行的线程以及重新执行顺序执行
公开(公告)号：US20100269102A1
公开(公告)日：2010-10-21
申请号：US12624804
申请日：2009-11-24
申请人： Fernando Latorre , Josep M. Codina , Enric Gibert Codina , Pedro Lopez , Carlos Madriles , Alejandro Martinez Vincente , Raul Martinez , Antonio Gonzalez
发明人： Fernando Latorre , Josep M. Codina , Enric Gibert Codina , Pedro Lopez , Carlos Madriles , Alejandro Martinez Vincente , Raul Martinez , Antonio Gonzalez
IPC分类号： G06F9/30 , G06F12/08 , G06F9/44
CPC分类号： G06F9/3842 , G06F8/433 , G06F8/452 , G06F8/457 , G06F9/3851 , G06F9/3861
摘要： Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.
摘要翻译：描述用于将顺序程序分解成多个线程，执行这些线程以及重建线程的顺序执行的系统，方法和装置。多个数据高速缓存单元（DCU）存储推测执行的线程的本地退出指令。合并级别缓存（MLC）合并来自DCU的行的数据。核心内存一致性模块（ICMC）全局退出MLC中推测执行线程的指令。

7. 发明授权

US09158705B2 Stride-based translation lookaside buffer (TLB) prefetching with adaptive offset 有权
标题翻译：基于Stride的翻译后备缓冲器（TLB）预取与自适应偏移
公开(公告)号：US09158705B2
公开(公告)日：2015-10-13
申请号：US13799582
申请日：2013-03-13
申请人： Jaroslaw Topp , Pedro Lopez , Fernando Latorre , Demos Pavlou , Thang Vu
发明人： Jaroslaw Topp , Pedro Lopez , Fernando Latorre , Demos Pavlou , Thang Vu
IPC分类号： G06F12/00 , G06F12/10 , G06F12/08
CPC分类号： G06F12/1027 , G06F12/0862 , G06F2212/602 , G06F2212/6026 , G06F2212/654
摘要： A processing device implementing stride-based translation lookaside buffer (TLB) prefetching with adaptive offset is disclosed. A processing device of the disclosure includes a data prefetcher to generate a data prefetch address based on a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, and a TLB prefetch address computation component to generate a TLB prefetch address based on the linear address, the stride, the prefetch distance, or an adaptive offset. The processing device also includes a cross page detection component to determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and cause a TLB prefetch request to be written to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) based on the data prefetch address or the TLB prefetch address.
摘要翻译：公开了一种利用自适应偏移实现基于步幅翻译后备缓冲器（TLB）预取的处理装置。本公开的处理设备包括数据预取器，用于基于线性地址，步幅或预取距离生成数据预取地址，与数据预取请求相关联的数据预取地址以及TLB预取地址计算组件以产生基于线性地址，步幅，预取距离或自适应偏移的TLB预取地址。该处理设备还包括一个跨页检测组件，用于确定数据预取地址或TLB预取地址与与线性地址相关联的页边界交叉，并且使TLB预取请求被写入TLB请求队列，TLB预取基于数据预取地址或TLB预取地址来请求翻译线性页码（LPN）的地址。

8. 发明申请

US20140156976A1 METHOD, APPARATUS AND SYSTEM FOR SELECTIVE EXECUTION OF A COMMIT INSTRUCTION 审中-公开
标题翻译：方法，选择性执行委托指令的方法和系统
公开(公告)号：US20140156976A1
公开(公告)日：2014-06-05
申请号：US13995441
申请日：2011-12-22
申请人： Enric Gibert Codina , Josep M. Codina , Fernando Latorre , Pedro Marcuello , Pedro Lopez , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Christos E. Kotselidis , Marc Lupon , Carlos Madriles Gimeno , Grigorios Magklis , Alejandro Martinez Vicente , Raul Martinez , Daniel Ortega , Demos Pavlou , Kyriakos A. Stavrou , Georgios Tournavitis , Polychronis Xekalakis
发明人： Enric Gibert Codina , Josep M. Codina , Fernando Latorre , Pedro Marcuello , Pedro Lopez , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Christos E. Kotselidis , Marc Lupon , Carlos Madriles Gimeno , Grigorios Magklis , Alejandro Martinez Vicente , Raul Martinez , Daniel Ortega , Demos Pavlou , Kyriakos A. Stavrou , Georgios Tournavitis , Polychronis Xekalakis
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30087 , G06F9/30185 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： Techniques and mechanisms for a processor to determine whether a commit action is to be performed. In an embodiment, a processor performs operations to determine whether a commit instruction is for contingent performance of a commit action. In another embodiment, one or more conditions of processor state are evaluated in response to determining that the commit instruction is for contingent performance of the commit action, where the evaluation is performed to determine whether the commit action indicated by the commit instruction is to be performed.
摘要翻译：处理器确定是否执行提交动作的技术和机制。在一个实施例中，处理器执行操作以确定提交指令是否用于或然执行提交动作。在另一个实施例中，响应于确定提交指令用于提交动作的或然执行来评估处理器状态的一个或多个条件，其中执行评估以确定是否要执行由提交指令指示的提交动作。

9. 发明申请

US20100115247A1 REPLACEMENT POLICY FOR HOT CODE DETECTION 有权
标题翻译：替代热代码检测政策
公开(公告)号：US20100115247A1
公开(公告)日：2010-05-06
申请号：US12263418
申请日：2008-10-31
申请人： Pedro Lopez , F. Jesus Sanchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio Gonzalez
发明人： Pedro Lopez , F. Jesus Sanchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio Gonzalez
IPC分类号： G06F9/30 , G06F9/06
CPC分类号： G06F11/3419 , G06F11/3466 , G06F2201/81 , G06F2201/88 , G06F2201/885
摘要： Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.
摘要翻译：描述与热代码检测的替换策略有关的方法和装置。在一些实施例中，可以确定存储在存储单元中的多个条目中的哪个条目将被替换。这些条目可以对应于热代码，并且可以存储对应于热代码的年龄和执行频率信息。还描述和要求保护其他实施例。

10. 发明申请

US20150178246A1 PROCESSING DEVICE FOR PERFORMING CONVOLUTION OPERATIONS 有权
标题翻译：用于执行演习操作的处理装置
公开(公告)号：US20150178246A1
公开(公告)日：2015-06-25
申请号：US14136302
申请日：2013-12-20
申请人： Enric Herrero Abellanas , Marc Lupon , Ayose J. Falcon , Frederico C. Pratas , Fernando Latorre , Pedro Lopez
发明人： Enric Herrero Abellanas , Marc Lupon , Ayose J. Falcon , Frederico C. Pratas , Fernando Latorre , Pedro Lopez
IPC分类号： G06F17/15
CPC分类号： G06F17/15 , G06F17/153 , G06K9/4609 , G06K9/627 , G06N3/04
摘要： Systems and methods for performing convolution operations. An example processing system comprises: a processing core; and a convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, the convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array.
摘要翻译：执行卷积运算的系统和方法。一个示例处理系统包括：处理核心; 以及卷积器单元，用于对由二维阵列表示的多个输入数据元素应用卷积滤波器，所述卷积单元包括耦合到两组或多组锁存器的多个乘法器，其中每组锁存器将存储一个二维阵列的相应一维部分的多个数据元素。

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