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1. 发明授权

US07224625B2 Method and circuit arrangement for controlling write access to a semiconductor memory 有权
标题翻译：用于控制对半导体存储器的写访问的方法和电路装置
公开(公告)号：US07224625B2
公开(公告)日：2007-05-29
申请号：US11117698
申请日：2005-04-29
申请人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier , Christian Weis
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1027 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C11/4076 , G11C11/4096 , G11C2207/229
摘要： The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.
摘要翻译：本发明涉及一种用于控制对半导体存储器，特别是DDR图形存储器的写入访问的方法，其中多个数据分组被写入每个数据脉冲串的半导体存储器，其中写访问由写命令启动，要写入存储器的数据分组在数据选通写时钟控制信号的周期的控制下锁存，其中数据分组被交替地使用数据选通写时钟控制信号的相应下降沿和上升沿锁存，并且数据选通写时钟控制信号在写操作开始时具有定义的状态。本发明还涉及一种用于执行该方法的电路装置。

2. 发明申请

US20050254307A1 Method and circuit arrangement for controlling write access to a semiconductor memory 有权
标题翻译：用于控制对半导体存储器的写访问的方法和电路装置
公开(公告)号：US20050254307A1
公开(公告)日：2005-11-17
申请号：US11117698
申请日：2005-04-29
申请人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier , Christian Weis
IPC分类号： G11C7/00 , G11C7/10 , G11C7/22 , G11C11/34 , G11C11/407 , G11C11/4076 , G11C11/4096
CPC分类号： G11C7/22 , G11C7/1027 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C11/4076 , G11C11/4096 , G11C2207/229
摘要： The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.
摘要翻译：本发明涉及一种用于控制对半导体存储器，特别是DDR图形存储器的写入访问的方法，其中多个数据分组被写入每个数据脉冲串的半导体存储器，其中写访问由写命令启动，要写入存储器的数据分组在数据选通写时钟控制信号的周期的控制下锁存，其中数据分组被交替地使用数据选通写时钟控制信号的相应下降沿和上升沿锁存，并且数据选通写时钟控制信号在写操作开始时具有定义的状态。本发明还涉及一种用于执行该方法的电路装置。

3. 发明授权

US06670802B2 Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits 有权
公开(公告)号：US06670802B2
公开(公告)日：2003-12-30
申请号：US10033131
申请日：2001-10-22
申请人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schroegmeier , Christian Weis
发明人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schroegmeier , Christian Weis
IPC分类号： G01R3102
CPC分类号： G11C29/003
摘要： Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.

4. 发明授权

US06532188B2 Integrated memory having a row access controller for activating and deactivating row lines 有权
公开(公告)号：US06532188B2
公开(公告)日：2003-03-11
申请号：US10012161
申请日：2001-10-29
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Thilo Marx , Torsten Partsch , Sabine Kieser , Peter Schroegmeier , Michael Sommer , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Thilo Marx , Torsten Partsch , Sabine Kieser , Peter Schroegmeier , Michael Sommer , Christian Weis
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C8/10 , G11C8/18
摘要： An integrated memory is described which has a memory cell array with column lines and row lines. A row access controller serves for activating one of the row lines and for controlling a deactivation operation. An input of a control unit is connected to a signal terminal for a signal that, in the event of a read access to one of the memory cells, defines the beginning of data outputting to a point outside the memory cell array. The data output is synchronized with a clock signal. In this case, the signal is adjustable depending on an operating frequency of the memory. An output signal of the control unit serves for triggering the deactivation operation of one of the row lines after a write access. Therefore, in the event of a write access, a comparatively high data throughput is possible even at different operating frequencies of the integrated memory.

5. 发明申请

US20050219084A1 Integrated circuit with parallel-serial converter 审中-公开
标题翻译：并联串行转换器集成电路
公开(公告)号：US20050219084A1
公开(公告)日：2005-10-06
申请号：US11089039
申请日：2005-03-25
申请人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： Integrated circuit with a parallel-serial converter The invention relates to an integrated circuit and method for time-offset provision of input data for a parallel-serial converter, in particular for or in a DDR semiconductor memory, having at least n input terminals at which at least n data packets are present in parallel, a delay device arranged in a manner connected downstream of the input terminals, at least some of the data packets present on the input side being output in time-offset fashion with respect to one another by said delay device, a parallel-serial converter arranged in a manner connected downstream of the delay device, which parallel-serial converter performs a conversion of the data packets that are present in parallel and are time-offset with respect to one another into an output data signal comprising the time-offset data packets in serial form, and an output terminal for outputting the output data signal.
摘要翻译：具有并行串行转换器的集成电路技术领域本发明涉及一种用于时间偏移提供用于并行 - 串行转换器的输入数据的集成电路和方法，特别是用于或在DDR半导体存储器中的至少n个输入端子，并行存在至少n个数据分组，延迟装置以连接在输入端子下游的方式布置，存在于输入侧的数据分组中的至少一些以相对于彼此的时间偏移方式通过所述延迟装置，并联串行转换器，以与延迟装置下游相连的方式布置，该并行串行转换器对并行存在的并相对于彼此进行时间偏移的数据包进行转换，并将其转换为输出数据包括串行形式的时间偏移数据分组的信号和用于输出输出数据信号的输出端。

6. 发明授权

US07215263B2 Parallel-serial converter 有权
标题翻译：并行串行转换器
公开(公告)号：US07215263B2
公开(公告)日：2007-05-08
申请号：US11089034
申请日：2005-03-25
申请人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： The invention relates to a parallel-serial converter for converting parallel data into serial data, in particular for or in a DDR semiconductor memory, having at least n input terminals at which n data signals are present in parallel, an output terminal for outputting a serial data signal, a controllable latch connected to the input terminals on the input side, a common storage node, which is connected to outputs of the latch and which holds a data signal of the controllable latch present last, a controllable bypass device, which has an input, which is coupled to the storage node on the output side and which has a control terminal, via which a predeterminable state present at the input of the bypass device can be switched onto the storage node. The invention furthermore relates to a semiconductor memory having such a parallel-serial converter and to a method for operating such a parallel-serial converter.
摘要翻译：本发明涉及一种用于将并行数据转换为串行数据的并行数据转换器，特别是用于或在DDR半导体存储器中，具有并行存在n个数据信号的至少n个输入端，用于输出串行数据的输出端子数据信号，连接到输入侧的输入端的可控制锁存器，连接到锁存器的输出并保持最后存在的可控制锁存器的数据信号的公共存储节点，可控旁路装置，其具有输入，其耦合到输出侧的存储节点并且具有控制终端，通过该输入可以将存在于旁路设备的输入端的可预定状态切换到存储节点。本发明还涉及具有这种并行 - 串行转换器的半导体存储器以及用于操作这种并行 - 串行转换器的方法。

7. 发明申请

US20050270852A1 Read latency control circuit 有权
标题翻译：读延迟控制电路
公开(公告)号：US20050270852A1
公开(公告)日：2005-12-08
申请号：US11136712
申请日：2005-05-25
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
IPC分类号： G06F3/06 , G11C7/22 , G11C11/4076
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/20 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2272
摘要： The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.
摘要翻译：本发明提供了一种用于通过用于对半导体存储器的读取访问的基于FIFO的读延迟控制电路来设置和控制读延迟（L）的方法，具有提供公共内部时钟信号的方法步骤; 从公共时钟信号产生与第一时钟信号不同的内部第一时钟信号和内部第二时钟信号; 产生用于从所述第一时钟信号读出读取数据的输出指针; 生成用于从所述第二时钟信号读取所述读取数据的输入指针; 通过在输出指针和输入指针之间分配定义的，固定地预定的时间偏移来初始化输入和输出指针。本发明还提供了一种用于执行该方法的相应电路装置。

8. 发明授权

US07404018B2 Read latency control circuit 有权
标题翻译：读延迟控制电路
公开(公告)号：US07404018B2
公开(公告)日：2008-07-22
申请号：US11136712
申请日：2005-05-25
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/20 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2272
摘要： The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.
摘要翻译：本发明提供了一种用于通过用于对半导体存储器的读取访问的基于FIFO的读延迟控制电路来设置和控制读延迟（L）的方法，具有提供公共内部时钟信号的方法步骤; 从公共时钟信号产生与第一时钟信号不同的内部第一时钟信号和内部第二时钟信号; 产生用于从所述第一时钟信号读出读取数据的输出指针; 生成用于从所述第二时钟信号读取所述读取数据的输入指针; 通过在输出指针和输入指针之间分配定义的，固定地预定的时间偏移来初始化输入和输出指针。本发明还提供了一种用于执行该方法的相应电路装置。

9. 发明申请

US20050216623A1 Parallel-serial converter 有权
标题翻译：并行串行转换器
公开(公告)号：US20050216623A1
公开(公告)日：2005-09-29
申请号：US11089034
申请日：2005-03-25
申请人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
IPC分类号： G06F13/12 , G11C11/407 , G11C11/4093 , H03M9/00
CPC分类号： H03M9/00
摘要： The invention relates to a parallel-serial converter for converting parallel data into serial data, in particular for or in a DDR semiconductor memory, having at least n input terminals at which n data signals are present in parallel, an output terminal for outputting a serial data signal, a controllable latch connected to the input terminals on the input side, a common storage node, which is connected to outputs of the latch and which holds a data signal of the controllable latch present last, a controllable bypass device, which has an input, which is coupled to the storage node on the output side and which has a control terminal, via which a predeterminable state present at the input of the bypass device can be switched onto the storage node. The invention furthermore relates to a semiconductor memory having such a parallel-serial converter and to a method for operating such a parallel-serial converter.
摘要翻译：本发明涉及一种用于将并行数据转换为串行数据的并行数据转换器，特别是用于或在DDR半导体存储器中，具有并行存在n个数据信号的至少n个输入端，用于输出串行数据的输出端子数据信号，连接到输入侧的输入端的可控制锁存器，连接到锁存器的输出并保持最后存在的可控制锁存器的数据信号的公共存储节点，可控旁路装置，其具有输入，其耦合到输出侧的存储节点并且具有控制终端，通过该输入可以将存在于旁路设备的输入端的可预定状态切换到存储节点。本发明还涉及具有这种并行 - 串行转换器的半导体存储器以及用于操作这种并行 - 串行转换器的方法。

10. 发明授权

US06542389B2 Voltage pump with switch-on control 失效
公开(公告)号：US06542389B2
公开(公告)日：2003-04-01
申请号：US10046378
申请日：2001-10-19
申请人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schrögmeier , Christian Weis
发明人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schrögmeier , Christian Weis
IPC分类号： H02M307
CPC分类号： H02M3/07
摘要： The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a terminal for feeding in a supply voltage and the terminal for tapping off the boosted output voltage. After the voltage pump has started to operate, the boosted output voltage is decoupled from the supply voltage by the transistor. A changeover switch forwards the respective higher of the output voltage or supply voltage to the substrate terminal and gate terminal of the transistor. The switch-on control enables early provision of a boosted output voltage in conjunction with reliable start-up operation of the voltage pump, while the additional outlay on circuitry is minimized.

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