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1. 发明专利

JP2008166816A Dual-molded multi-chip package system 有权
标题翻译：双模多芯片包装系统
公开(公告)号：JP2008166816A
公开(公告)日：2008-07-17
申请号：JP2007339497
申请日：2007-12-28
申请人： Stats Chippac Ltd , スタッツ・チップパック・リミテッドStats Chippac Ltd.
发明人： RAMAKRISHNA KAMBHAMPATI , SHIM IL KWON , CHOW SENG GUAN
IPC分类号： H01L25/10 , H01L23/52 , H01L25/04 , H01L25/11 , H01L25/18
CPC分类号： H01L23/3128 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3135 , H01L23/49861 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/85 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/165 , H01L2224/12105 , H01L2224/24137 , H01L2224/32225 , H01L2224/45014 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/85 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a dual-molded multi-chip package system (2500). SOLUTION: A method for manufacturing a dual-molded multi-chip package system comprises a step of forming an embedded integrated circuit package system (200), having a first integrated circuit chip (102) and a first sealant covering a lead (110) connected to the first integrated circuit chip;a step of mounting a semiconductor device (216) on the first sealant (112) by connecting the lead; and a step of forming a second sealant (220) on the semiconductor device (216) and the embedded integrated circuit package system (202). COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供双模多芯片封装系统（2500）。解决方案：一种用于制造双重模制多芯片封装系统的方法，包括形成嵌入式集成电路封装系统（200）的步骤，该嵌入式集成电路封装系统具有第一集成电路芯片（102）和覆盖引线 110）连接到所述第一集成电路芯片;通过连接所述引线将半导体器件（216）安装在所述第一密封剂（112）上的步骤; 以及在半导体器件（216）和嵌入式集成电路封装系统（202）上形成第二密封剂（220）的步骤。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2006324666A OFFSET INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM 审中-公开
公开(公告)号：JP2006324666A
公开(公告)日：2006-11-30
申请号：JP2006136761
申请日：2006-05-16
申请人： STATS CHIPPAC LTD
发明人： SHIM IL KWON , HAN BYUNG JOON , CHOW SENG GUAN
IPC分类号： H01L25/18 , H01L25/10 , H01L25/11
摘要： PROBLEM TO BE SOLVED: To provide a means capable of inspecting an actual failure mode of each integrated circuit and improving density and miniaturization of the integrated circuit. SOLUTION: An offset integrated circuit package-on-package stacking system 100 includes: providing a base substrate; providing an array of contact pads on the base substrate; mounting an active component and an optional passive component 104 on the base substrate; injecting a mold cap 106 to the base substrate; mounting an offset package (108) on the base substrate and the mold cap (106); and separating a package-on-package from the base substrate. COPYRIGHT: (C)2007,JPO&INPIT

3. 发明专利

JP2006324665A OFFSET INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM 审中-公开
公开(公告)号：JP2006324665A
公开(公告)日：2006-11-30
申请号：JP2006136747
申请日：2006-05-16
申请人： STATS CHIPPAC LTD
发明人： SHIM IL KWON , HAN BYUNG JOON , CHOW SENG GUAN
IPC分类号： H01L25/18 , H01L25/10 , H01L25/11
摘要： PROBLEM TO BE SOLVED: To provide a means capable of inspecting an actual failure mode of this integrated circuit and improving density and miniaturization of the integrated circuit. SOLUTION: An offset integrated circuit package-on-package stacking system 100 includes: providing a base substrate 104; forming a contact pad 119 on the base substrate 104; mounting a first integrated circuit 110 on the base substrate 104; forming a base package body 116 so as to surround the first integrated circuit 110; providing an offset substrate 122; mounting a second integrated circuit 128 on the offset substrate 122; placing the offset substrate 122 on the base package body 116 and coupling the offset substrate 122 to the contact pad 119. COPYRIGHT: (C)2007,JPO&INPIT

4. 发明申请

WO2006118720A3 SEMICONDUCTOR ASSEMBLY INCLUDING CHIP SCALE PACKAGE AND SECOND SUBSTRATE AND HAVING EXPOSED SUBSTRATE SURFACES ON UPPER AND LOWER SIDES 审中-公开
标题翻译：半导体组件，包括芯片尺寸封装和第二基板，并在上下表面具有暴露的基板表面
公开(公告)号：WO2006118720A3
公开(公告)日：2007-04-19
申请号：PCT/US2006011712
申请日：2006-03-31
申请人： STATS CHIPPAC LTD , KARNEZOS MARCOS , SHIM IL KWON , HAN BYUNG JOON , RAMAKRISHNA KAMBHAMPATI , CHOW SENG GUAN
发明人： KARNEZOS MARCOS , SHIM IL KWON , HAN BYUNG JOON , RAMAKRISHNA KAMBHAMPATI , CHOW SENG GUAN
IPC分类号： H01L21/44
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/3135 , H01L23/49575 , H01L23/49833 , H01L23/552 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/162 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06568 , H01L2225/06572 , H01L2225/06586 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second ("land") side, mounted over the molding of the first package with the first side of the second substrate facing the die attach side of the first package substrate. Accordingly, the die attach sides of the first substrate and the first side of the second substrate face one another, and the "land" sides of the substrates face away from one another. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated in such a way that both the land side of the second substrate (one side of the assembly) and a portion of the land side of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package. Also, methods for making such stacked packages assemblies include steps of providing singulated CSP; applying an adhesive onto the surface of the molding of the CSP; providing a second substrate having first and second sides; inverting the CSP and placing the inverted CSP onto the first side of the second substrate such that the adhesive contacts the first side of the second substrate; curing the adhesive; performing a plasma clean; wire bonding to form z-interconnection between the first side of the second substrate and the land side of the CSP; performing a plasma clean; performing a molding operation to enclose the first side of the second substrate, the z-interconnection wire bonds and wire loops, the edges of the CSP, and the marginal area on the land side of the CSP, leaving exposed the land side of the second substrate and an area of the land side of the CSP substrate located within a marginal area; attaching second level interconnect solder balls to sites on exposed area of the CSP substrate; and (where the second substrate was provided in a strip or array) saw singulating to complete the assembly. In some embodiments one or more additional components are stacked over the land side of the second substrate.
摘要翻译：半导体组件包括：第一封装，每个封装具有至少一个管芯，其固定到第一封装衬底的管芯附着侧并与之电互连，以及具有第一侧面和第二（“焊盘”）侧的第二衬底，在第一封装的模制中，第二衬底的第一面面向第一封装衬底的裸片附着侧。因此，第一基板的芯片附着侧和第二基板的第一面彼此面对，并且基板的“平台”侧面彼此背离。封装和基板的Z形互连是通过连接第一和第二基板的引线键合。该组件以这样一种方式封装，使得第二基板的接地侧（组件的一侧）和第一封装基板的陆部侧的一部分（在组件的相对侧）被露出，使得可以进行二级互连和与附加组件的互连。在一些实施例中，第一封装是芯片级封装。此外，制造这种堆叠包装组件的方法包括提供单独的CSP的步骤; 将粘合剂施加到CSP的模制品的表面上; 提供具有第一和第二侧面的第二基板; 反转CSP并将反转的CSP放置在第二衬底的第一侧上，使得粘合剂接触第二衬底的第一侧; 固化粘合剂; 进行等离子清洁引线接合以在第二基板的第一侧和CSP的接地侧之间形成z-互连; 进行等离子清洁执行模制操作以包围第二基板的第一侧，z互连线接合和线环，CSP的边缘以及CSP的陆侧上的边缘区域，从而暴露第二基板的接地侧基板和位于边缘区域内的CSP基板的陆侧的区域; 将第二级互连焊球连接到CSP基板的暴露区域上的位置; 和（其中第二基底设置在条或阵列中）锯切单体以完成组装。在一些实施例中，一个或多个附加部件堆叠在第二基板的陆侧上。

5. 发明申请

WO2006105514A3 SEMICONDUCTOR STACKED PACKAGE ASSEMBLY HAVING EXPOSED SUBSTRATE SURFACES ON UPPER AND LOWER SIDES 审中-公开
标题翻译：半导体堆叠封装组件在上下表面具有暴露的基板表面
公开(公告)号：WO2006105514A3
公开(公告)日：2007-09-20
申请号：PCT/US2006012394
申请日：2006-03-31
申请人： STATS CHIPPAC LTD , KARNEZOS MARCOS , SHIM IL KWON , HAN BYUNG JOON , RAMAKRISHNA KAMBHAMPATI , CHOW SENG GUAN
发明人： KARNEZOS MARCOS , SHIM IL KWON , HAN BYUNG JOON , RAMAKRISHNA KAMBHAMPATI , CHOW SENG GUAN
IPC分类号： H01L23/538
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/552 , H01L24/73 , H01L25/03 , H01L25/105 , H01L25/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2224/85013 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/01013 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H01L2924/1815 , H01L2924/19105 , H01L2924/19106 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other; that is, the die attach sides of the package substrates face one another, and the "land' sides of the substrates face away from one another. Z-lnterconnectio of the packages is by wire bonds connecting the first and second package substrates. The assembly is encapsulated in such a way th both the second package substrate (one side of the assembly) and a portion of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package, and the second package is a land grid array package.
摘要翻译：堆叠的封装组件包括第一和第二堆叠封装，每个封装具有至少一个管芯，该裸管固定到封装衬底的管芯附着侧并与其电连接。一个包相对于另一个倒转; 也就是说，封装基板的芯片附接面彼此面对，并且基板的“平台”侧面彼此背离，封装的Z形连接通过连接第一和第二封装基板的引线接合，组件以这样的方式封装第二封装衬底（组件的一侧）和第一封装衬底的一部分（在组件的相对侧上），使得第二级互连和与附加部件的互连可以在一些实施例中，第一封装是芯片级封装，第二封装是焊盘栅阵列封装。

6. 发明专利

SG10201506143RA SEMICONDUCTOR DEVICE AND METHOD OF FORMING DOUBLE-SIDEDFAN-OUT WAFER LEVEL PACKAGE 未知
公开(公告)号：SG10201506143RA
公开(公告)日：2016-03-30
申请号：SG10201506143R
申请日：2015-08-05
申请人： STATS CHIPPAC LTD
发明人： SHIM IL KWON , MARIMUTHU PANDI C , CHOI WON KYOUNG , GOH SZE PING , CAPARAS JOSE A
摘要： A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.

7. 发明专利

SG2014010557A SEMICONDUCTOR DEVICE AND METHOD OF BONDING DIFFERENT SIZESEMICONDUCTOR DIE AT THE WAFER LEVEL 未知
公开(公告)号：SG2014010557A
公开(公告)日：2014-04-28
申请号：SG2014010557
申请日：2011-09-22
申请人： STATS CHIPPAC LTD
发明人： KOO JUN MO , MARIMUTHU PANDI C , YOON SEUNG WOOK , SHIM IL KWON
摘要： A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.

8. 发明专利

SG2013051404A SEMICONDUCTOR DEVICE AND METHOD OF USING SUBSTRATE HAVING BASE AND CONDUCTIVE POSTS TO FORM VERTICAL INTERCONNECT STRUCTURE IN EMBEDDED DIE PACKAGE 未知
公开(公告)号：SG2013051404A
公开(公告)日：2014-04-28
申请号：SG2013051404
申请日：2013-07-02
申请人： STATS CHIPPAC LTD
发明人： SHIM IL KWON , KOO JUN MO , MARIMUTHU PANDI C , LIN YAOJIAN , LIM SEE CHIAN

9. 发明专利

SG188713A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DIE WITH ACTIVE REGION RESPONSIVE TO EXTERNAL STIMULUS 未知
公开(公告)号：SG188713A1
公开(公告)日：2013-04-30
申请号：SG2012058285
申请日：2012-08-06
申请人： STATS CHIPPAC LTD
发明人： HAN BYUNG JOON , SHIM IL KWON , KUAN HEAP HOE
摘要： Abstract SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DIE WITH ACTIVE REGION RESPONSIVE TO EXTERNAL STIMULUSA semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor. An encapsulant is deposited over the first semiconductor die. A conductive layer is formed over the encapsulant and firstsemiconductor die. An insulating layer can be formed over the first semiconductor die. An opening is formed in the insulating layer over the active region. A transmissive layer is formed over the first semiconductor die including the active region. The transmissive layer includes an optical dielectric material or an optical transparent or translucent material. The active region is responsive to an external stimulus passing through the transmissive Layer. A plurality of bumps is formed through the encapsulant and electrically connected to the conductive Layer. A second semiconductor die is disposed adjacent to the first semiconductor die. (Fig 5)

10. 发明专利

SG179385A1 SEMICONDUCTOR DEVICE AND METHOD OF BONDING DIFFERENT SIZE SEMICONDUCTOR DIE AT THE WAFER LEVEL 未知
公开(公告)号：SG179385A1
公开(公告)日：2012-04-27
申请号：SG2011068475
申请日：2011-09-22
申请人： STATS CHIPPAC LTD
发明人： KOO JUN MO , MARIMUTHU PANDI C , YOON SEUNG WOOK , SHIM IL KWON
摘要： Abstract SEMICONDUCTOR DEVICE AND METHOD OF BONDING DIFFERENT SIZE SEMICONDUCTOR DIE AT THE WAFER LEVELA semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.(Fig. 6)

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