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1. 发明申请

WO2006028693A2 STACKED INTEGRATED CIRCUIT CASCADE SIGNALING SYSTEM AND METHOD 审中-公开
标题翻译：堆叠集成电路CASCADE信号系统与方法
公开(公告)号：WO2006028693A2
公开(公告)日：2006-03-16
申请号：PCT/US2005/029867
申请日：2005-08-23
申请人： STAKTEK GROUP L.P. , CADY, James , RAPPORT, Russell , WILDER, James
发明人： CADY, James , RAPPORT, Russell , WILDER, James
IPC分类号： H01L23/02
CPC分类号： H01L25/105 , H01L23/4985 , H01L2225/107 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Integrated circuits (ICs) are stacked into modules that conserve PCB or other board surface area. The modules provide for lower capacitance memory signaling systems and methods for connecting stacked CSPs in a serial cascade arrangement. In one preferred embodiment, on-die terminations are used selectively to terminate a cascaded series of conductive paths. In another preferred embodiment, a form standard provides a physical form that allows many of the varying package sizes found in a broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.
摘要翻译：集成电路（IC）堆叠成可以节省PCB或其他板表面积的模块。这些模块提供了较低电容存储器信号系统和用于以串联级联布置连接堆叠CSP的方法。在一个优选实施例中，选择性地使用管芯端子来终止级联的导电路径。在另一个优选实施例中，形式标准提供了一种物理形式，其允许在采用标准连接柔性电路设计的同时，在宽范围的CSP封装系列中发现许多变化的封装尺寸。

2. 发明申请

WO2004112128A2 LOW PROFILE STACKING SYSTEM AND METHOD 审中-公开
标题翻译：低配置文件堆栈系统和方法
公开(公告)号：WO2004112128A2
公开(公告)日：2004-12-23
申请号：PCT/US2004/016347
申请日：2004-05-25
申请人： STAKTEK GROUP, L.P. , CADY, James , PARTRIDGE, Julian , WEHRLY, James, JR. , ROPER, David , BUCHLE, Jeff
发明人： CADY, James , PARTRIDGE, Julian , WEHRLY, James, JR. , ROPER, David , BUCHLE, Jeff
IPC分类号： H01L23/00
CPC分类号： H05K1/141 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73253 , H01L2224/81801 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01322 , H01L2924/19041 , H01L2924/3011 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , Y10T29/49126 , Y10T29/49144
摘要： The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing such mounted devices for stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
摘要翻译：本发明提供一种将集成电路器件安装到衬底上的系统和方法，以及用于使用这种安装的器件用于堆叠模块的系统和方法。封装的集成电路器件的接触焊盘基本上露出。将包括较高温度的焊膏合金的焊膏施加到要安装的基板或集成电路器件上。集成电路器件定位成与衬底的触点接触。施加热量以在基板的触点和集成电路装置之间形成高温接头，从而形成具有高温接头的装置 - 基板组件。形成的接头在随后的加工步骤中较少受到再熔化。该方法可以用于设计堆叠的模块结构，例如根据本发明的优选实施例中所公开的那些。通常，创建的关节的轮廓较低。

3. 发明公开

EP1730774A2 INTEGRATED CIRCUIT STACKING SYSTEM AND METHOD 审中-公开
标题翻译：堆叠系统和方法用于集成电路
公开(公告)号：EP1730774A2
公开(公告)日：2006-12-13
申请号：EP05735041.5
申请日：2005-03-30
申请人： Staktek Group, L.P.
发明人： CADY, James , WILDER, James , ROPER, David , WEHRLY, JR., Douglas
IPC分类号： H01L23/02 , H01L23/34 , H01L23/10
CPC分类号： H01L23/3114 , H01L23/4985 , H01L23/5386 , H01L23/5387 , H01L25/105 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/06589 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/16225 , H01L2924/00012 , H01L2224/0401
摘要： The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules 10 provided herewith. In a preferred embodiment in accordance with the invention, a form standard 34 provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design 32. In a preferred embodiment, the form standard 34 will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard 34 may include a heat spreader portion 192 with mounting feet 198. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module 10 to reduce the loading effect upon data signals in memory access.

4. 发明申请

WO2005114726A3 STACKED MODULE SYSTEMS AND METHODS 审中-公开
公开(公告)号：WO2005114726A3
公开(公告)日：2005-12-01
申请号：PCT/US2005/016764
申请日：2005-05-11
申请人： STAKTEK GROUP L.P. , WEHRLY, Douglas, Jr. , CADY, James , PARTRIDGE, Julian , ROPER, David
发明人： WEHRLY, Douglas, Jr. , CADY, James , PARTRIDGE, Julian , ROPER, David
IPC分类号： H01L23/02
摘要： The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or more conductive layers with preferred embodiments having two conductive layers. A form standard is disposed along the lower planar surface and extends laterally beyond the package of one or more CSPs in a stacked module. The form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be comprised of heat conductive material such as copper, for example.

5. 发明申请

WO2006028643A2 CIRCUIT MODULE SYSTEM AND METHOD 审中-公开
标题翻译：电路模块系统和方法
公开(公告)号：WO2006028643A2
公开(公告)日：2006-03-16
申请号：PCT/US2005/028547
申请日：2005-08-10
申请人： STAKTEK GROUP L.P. , GOODWIN, Paul , CADY, James , WEHRLY, James, Douglas, Jr.
发明人： GOODWIN, Paul , CADY, James , WEHRLY, James, Douglas, Jr.
IPC分类号： H05K7/06 , H05K7/10
CPC分类号： H05K1/189 , G11C5/04 , H01L25/105 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H05K1/0203 , H05K1/118 , H05K1/181 , H05K3/0061 , H05K2201/056 , H05K2201/1056 , H05K2201/10734 , H05K2201/2018 , H05K2203/1572 , H01L2224/0401
摘要： Flexible circuitry is populated with integrated circuits (ICs) disposed along one or both of its major sides. Contacts distributed along the flexible circuitry provide connection to the ICs. Preferably, the flexible circuitry is disposed about an edge of a rigid, thermally-conductive substrate thus placing the integrated circuitry on one or both sides of the substrate with one or two layers of integrated circuitry on one or both sides of the substrate. In alternative, but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may remove substrate material to reduce module profile. In preferred embodiments, the contacts distributed along the flexible circuitry are configured for insertion into an edge connector socket such as those found in general purpose and server computers. Preferred substrates are comprised of thermally conductive material. Extensions from the substrate in preferred embodiments can be expected to reduce thermal module loading and encourage reduced thermal variations amongst the integrated circuits of the module during operation.
摘要翻译：灵活的电路填充有沿其主要一侧或两侧设置的集成电路（IC）。沿柔性电路分布的触点提供与IC的连接。优选地，柔性电路围绕刚性的导热基底的边缘设置，因此将集成电路置于衬底的一侧或两侧，在衬底的一侧或两侧上具有一层或两层集成电路。在替代方案中，也是优选实施例中，最靠近基板的柔性电路侧的IC至少部分地设置在基板中的窗口，凹穴或切口区域中。其他实施例可以仅填充柔性电路的一侧或者可以移除衬底材料以减少模块轮廓。在优选实施例中，沿着柔性电路分布的触点被配置为插入到诸如在通用和服务器计算机中找到的边缘连接器插座中。优选的衬底由导热材料构成。预期在优选实施例中，来自衬底的延伸可以减少热模块负载并且促进在操作期间模块的集成电路之间的热变化减小。

6. 发明申请

WO2005098941A2 INTEGRATED CIRCUIT STACKING SYSTEM AND METHOD 审中-公开
标题翻译：集成电路堆栈系统及方法
公开(公告)号：WO2005098941A2
公开(公告)日：2005-10-20
申请号：PCT/US2005/010756
申请日：2005-03-30
申请人： STAKTEK GROUP L.P. , CADY, James , WILDER, James , ROPER, David , WEHRLY, JR., Douglas
发明人： CADY, James , WILDER, James , ROPER, David , WEHRLY, JR., Douglas
IPC分类号： H01L23/02
CPC分类号： H01L23/3114 , H01L23/4985 , H01L23/5386 , H01L23/5387 , H01L25/105 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/06589 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/16225 , H01L2924/00012 , H01L2224/0401
摘要： The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard may include a heat spreader portion with mounting feet. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
摘要翻译：本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。在替代实施例中，形式标准可以包括具有安装支脚的散热器部分。在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

7. 发明申请

WO2005010990A2 POINT TO POINT MEMORY EXPANSION SYSTEM AND METHOD 审中-公开
标题翻译：要点内存扩展系统和方法
公开(公告)号：WO2005010990A2
公开(公告)日：2005-02-03
申请号：PCT/US2004/023152
申请日：2004-07-20
申请人： STAKTEK GROUP, L.P. , CADY, James , RAPPORT, Russell , PARTRIDGE, Julian , WEHRLY, James, Jr. , WILDER, James , ROPER, David , BUCHLE, Jeff
发明人： CADY, James , RAPPORT, Russell , PARTRIDGE, Julian , WEHRLY, James, Jr. , WILDER, James , ROPER, David , BUCHLE, Jeff
IPC分类号： H01L25/10
CPC分类号： H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16237 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2924/01322 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734
摘要： With the use of stacked modules, a system and method for point to point addressing of multiple integrated memory circuits is provided. A single memory expansion board is populated with stacked modules of integrated circuits. The single memory expansion board is located at the terminus of a transmission line, thus, effectively placing at a relative single point in the addressing system, added memory capacity that would otherwise have required multiple memory expansion boards and, consequently, a longer bus. Therefore, signal degradation issues are mitigated and the system has improved tolerance for higher signal speeds with added memory capacity. In a preferred embodiment, a four DIMM socket memory access bus that does not employ stacking is replaced with a single DIMM socket bus that supports stacking up to four high on a single DIMM. Although the present invention is preferably employed to advantage using stacked modules comprised from multiple CSPs, it may be employed with modules comprised from any number and type of integrated circuits including any type of packaging, whether CSP or leaded.
摘要翻译：通过使用堆叠模块，提供了用于多个集成存储器电路的点对点寻址的系统和方法。单个存储器扩展板上装有集成电路的堆叠模块。单个存储器扩展板位于传输线的终点处，因此，有效地放置在寻址系统中的相对单个点处，增加了否则将需要多个存储器扩展板的存储器容量，并且因此需要更长的总线。因此，信号降级问题得到缓解，并且具有增加的存储容量的系统已经改善了对更高信号速度的容限。在优选实施例中，不使用堆叠的四个DIMM插槽存储器存取总线被单个DIMM插槽总线替代，该DIMM插槽总线在单个DIMM上支持堆叠高达四个高。虽然本发明优选地使用由多个CSP组成的堆叠模块，但是可以使用包括任何数量和类型的集成电路的模块，包括任何类型的封装，不管是CSP还是带引线。

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