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1. 发明申请

US20140181476A1 Scheduler Implementing Dependency Matrix Having Restricted Entries 审中-公开
标题翻译：调度器实现具有限制条目的依赖矩阵
公开(公告)号：US20140181476A1
公开(公告)日：2014-06-26
申请号：US13723684
申请日：2012-12-21
申请人： Srikanth T. Srinivasan , Matthew C. Merten , Bambang Sutanto , Rahul R. Kulkarni , Justin M. Deinlein , James D. Hadley
发明人： Srikanth T. Srinivasan , Matthew C. Merten , Bambang Sutanto , Rahul R. Kulkarni , Justin M. Deinlein , James D. Hadley
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction.
摘要翻译：公开了实现具有限制条目的依赖矩阵的调度器。本公开的处理装置包括：解码单元，用于对指令进行解码;以及可通信地耦合到解码单元的调度器。在一个实施例中，调度器被配置为接收解码的指令，确定解码的指令限定为由调度器维护的依赖矩阵中的受限保留站（RS）条目类型的分配，识别依赖矩阵中的RS条目将所识别的空闲RS条目中的一个分配给依赖矩阵中的解码指令的信息，并且通过解码指令的源依赖性信息更新与所要求的RS条目相对应的依赖矩阵的一行。

2. 发明授权

US10235180B2 Scheduler implementing dependency matrix having restricted entries 有权
公开(公告)号：US10235180B2
公开(公告)日：2019-03-19
申请号：US13723684
申请日：2012-12-21
申请人： Srikanth T. Srinivasan , Matthew C. Merten , Bambang Sutanto , Rahul R. Kulkarni , Justin M. Deinlein , James D. Hadley
发明人： Srikanth T. Srinivasan , Matthew C. Merten , Bambang Sutanto , Rahul R. Kulkarni , Justin M. Deinlein , James D. Hadley
IPC分类号： G06F9/30 , G06F9/38
摘要： A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler communicably coupled to the decode unit. In one embodiment, the scheduler is configured to receive the decoded instruction, determine that the decoded instruction qualifies for allocation as a restricted reservation station (RS) entry type in a dependency matrix maintained by the scheduler, identify RS entries in the dependency matrix that are free for allocation, allocate one of the identified free RS entries with information of the decoded instruction in the dependency matrix, and update a row of the dependency matrix corresponding to the claimed RS entry with source dependency information of the decoded instruction.

3. 发明申请

US20130339689A1 LATER STAGE READ PORT REDUCTION 审中-公开
标题翻译：后期阅读端口减少
公开(公告)号：US20130339689A1
公开(公告)日：2013-12-19
申请号：US13993546
申请日：2011-12-29
申请人： Srikanth T. Srinivasan , Chia Yin Kevin Lai , Bambang Sutanto , Chad D. Hancock
发明人： Srikanth T. Srinivasan , Chia Yin Kevin Lai , Bambang Sutanto , Chad D. Hancock
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/30141 , G06F9/3828
摘要： In some implementations, a register file has a plurality of read ports for providing data to a micro-operation during execution of the micro-operation. For example, the micro-operation may utilize at least two data sources, with at least one first data source being utilized at least one pipeline stage earlier than at least one second data source. A number of register file read ports may be allocated for executing the micro-operation. A bypass calculation is performed during a first pipeline stage to detect whether the at least one second data source is available from a bypass network. During a subsequent second pipeline stage, when the at least one second data source is detected to be available from the bypass network, the number of the read ports allocated to the micro-operation may be reduced.
摘要翻译：在一些实现中，寄存器文件具有多个读端口，用于在执行微操作期间向微操作提供数据。例如，微操作可以利用至少两个数据源，其中至少一个第一数据源被使用在比至少一个第二数据源更早的至少一个流水线级。可以分配多个寄存器文件读取端口用于执行微操作。在第一流水线阶段期间执行旁路计算，以检测至少一个第二数据源是否可用于旁路网络。在随后的第二流水线阶段期间，当检测到至少一个第二数据源从旁路网络可用时，可以减少分配给微操作的读取端口的数量。

4. 发明申请

US20140195790A1 PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
标题翻译：具有分支机构错误预测的第二个执行单元的处理程序
公开(公告)号：US20140195790A1
公开(公告)日：2014-07-10
申请号：US13994676
申请日：2011-12-28
申请人： Matthew C. Merten , Avinash Sodani , Sean P. Mirkes , Vijaykumar B. Kadgi , Bambang Sutanto , Chia Yin Kevin Lai , Morris Marden , Alexandre J. Farcy
发明人： Matthew C. Merten , Avinash Sodani , Sean P. Mirkes , Vijaykumar B. Kadgi , Bambang Sutanto , Chia Yin Kevin Lai , Morris Marden , Alexandre J. Farcy
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3851 , G06F9/3861 , G06F9/3867 , G06F9/3885
摘要： A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances.
摘要翻译：次级跳转执行单元（JEU）并入微处理器以与主JEU同时操作，使得能够执行同时分支操作，并可能检测到多个分支错误预测。当在同一个指令周期中对两个JEU执行分支操作时，辅助JEU的错误预测处理被划分到主JEU的调度流水线中，使得辅助JEU的分支处理在主JEU的分支处理之后发生，而初级JEU不处理分支。此外，在从处理器的重新排序缓冲器接收到nuke命令的情况下，进一步延迟用于辅助JEU的分支处理，以适应主JEU上的nuke的处理。进一步的实施方案支持促进联合联合国次级方案在某些情况下获得主要联合执行机构的错误预测机制。

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