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1. 发明授权

US06236249B1 Power-on reset circuit for a high density integrated circuit 失效
标题翻译：用于高密度集成电路的上电复位电路
公开(公告)号：US06236249B1
公开(公告)日：2001-05-22
申请号：US09333195
申请日：1999-06-14
申请人： Soo-Hwan Choi , Jong-Mia Park
发明人： Soo-Hwan Choi , Jong-Mia Park
IPC分类号： H03L700
CPC分类号： H03K17/284 , H03K17/223 , H03K2217/0036
摘要： A power-on reset circuit reduces power consumption and layout area by utilizing a time delay to deactivate a reset circuit and clamp a reset signal a period of time after a power supply voltage has reached a predetermined level. The reset circuit includes a reset signal generator which maintains the reset signal in an active state until the power supply voltage has reached the predetermined level. The reset signal generator then deactivates the reset signal which causes a delay circuit to begin a time delay after which a delay signal is asserted. The delay signal deactivates a comparator in the reference voltage generator, a voltage detector, and a reset signal generator within the reset circuit, thereby reducing power consumption. The delay signal also activates a clamp circuit which clamps the reset signal to an inactive state.
摘要翻译：上电复位电路通过在电源电压达到预定电平之后的一段时间内利用时间延迟来去激活复位电路并钳位复位信号来降低功耗和布局面积。复位电路包括复位信号发生器，其将复位信号保持在有效状态，直到电源电压达到预定电平。复位信号发生器然后使复位信号无效，该复位信号使得延迟电路开始延时，此后延迟信号被断言。延迟信号使复位电路中的参考电压发生器，电压检测器和复位信号发生器中的比较器失效，由此降低功耗。延迟信号还激活钳位电路，钳位电路将复位信号钳位到无效状态。

2. 发明申请

US20050018480A1 Flash memory pipelined burst read operation circuit, method, and system 有权
标题翻译：闪存流水线突发读操作电路，方法和系统
公开(公告)号：US20050018480A1
公开(公告)日：2005-01-27
申请号：US10852841
申请日：2004-05-24
申请人： Soo-Hwan Choi , Jung-Hoon Park
发明人： Soo-Hwan Choi , Jung-Hoon Park
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C16/26
摘要： Method and apparatus for use with flash memory devices and systems are included among the embodiments. In exemplary systems, a pipelined burst read operation allows the device to support higher data transfer rates than are possible with prior art burst read flash memory devices. Preferably, the flash memory device supports both non-pipelined and pipelined read operations, with the read mode settable from a memory controller. Other embodiments are described and claimed.
摘要翻译：在实施例中包括用于闪存设备和系统的方法和装置。在示例性系统中，流水线突发读取操作允许设备支持比现有技术的突发读取闪存设备可能的更高的数据传输速率。优选地，闪存设备支持非流水线和流水线读取操作，读取模式可从存储器控制器设置。描述和要求保护其他实施例。

3. 发明申请

US20110252189A1 METHOD FOR GENERATING PHYSICAL IDENTIFIER IN STORAGE DEVICE AND MACHINE-READABLE STORAGE MEDIUM 有权
标题翻译：在存储设备和机器可读存储介质中生成物理标识符的方法
公开(公告)号：US20110252189A1
公开(公告)日：2011-10-13
申请号：US13085052
申请日：2011-04-12
申请人： Bo-Gyeong KANG , Jung-Wan Ko , Soo-Hwan Choi , Sung-Hee Hwang , Byung-Rae Lee
发明人： Bo-Gyeong KANG , Jung-Wan Ko , Soo-Hwan Choi , Sung-Hee Hwang , Byung-Rae Lee
IPC分类号： G06F12/00
CPC分类号： G11C16/3418 , G06F12/0246 , G06F2212/7209 , G11B20/00115 , G11B20/00963 , G11B2220/60 , G11C16/00 , G11C16/20 , G11C16/349 , G11C29/42 , G11C29/44 , G11C2029/4402
摘要： A method and system for generating a physical identifier in a storage device that includes a plurality of storage regions is provided. The method includes determining a number of reference storage regions for uniquely identifying the storage device; comparing the number of reference storage regions to a threshold; generating auxiliary storage regions for uniquely identifying the storage device, such that a number of the auxiliary storage regions corresponds to a result of the comparison; generating location distribution information of the reference storage regions and auxiliary storage regions; and storing the location distribution information in the storage device.
摘要翻译：提供了一种用于在包括多个存储区域的存储设备中生成物理标识符的方法和系统。该方法包括确定用于唯一地识别存储设备的参考存储区域的数量; 将参考存储区域的数量与阈值进行比较; 产生用于唯一地识别存储设备的辅助存储区域，使得多个辅助存储区域对应于比较的结果; 产生参考存储区域和辅助存储区域的位置分布信息; 以及将所述位置分发信息存储在所述存储装置中。

4. 发明授权

US06272051B1 Nonvolatile semiconductor memory device having a reference cell array 失效
标题翻译：具有参考单元阵列的非易失性半导体存储器件
公开(公告)号：US06272051B1
公开(公告)日：2001-08-07
申请号：US09474877
申请日：1999-12-29
申请人： Soo-Hwan Choi
发明人： Soo-Hwan Choi
IPC分类号： G11C1604
CPC分类号： G11C16/28
摘要： A semiconductor memory device having a plurality of reference cells for detecting states of and verifying written data in plurality of memory cells includes a memory cell array formed of the plurality of memory cells and a reference cell array formed of a plurality of units, each unit formed of the plurality of reference cells, reference cell having a same size as that of each memory cell. A sense amplifier circuit detects a difference between current flowing through a memory cell and a corresponding reference cell. Each unit in the reference cell array is formed of a plurality of the reference cells serially connected between the sense amplifier circuit and a control circuit for controlling the reference cells.
摘要翻译：具有多个参考单元的半导体存储器件，用于检测多个存储器单元中的写入数据的状态和验证，包括由多个存储单元形成的存储单元阵列和由多个单元形成的参考单元阵列，每个单元形成多个参考单元的参考单元具有与每个存储单元的尺寸相同的尺寸。感测放大器电路检测流过存储器单元的电流与相应的参考单元之间的差异。参考单元阵列中的每个单元由串联连接在读出放大器电路和用于控制参考单元的控制电路之间的多个参考单元形成。

5. 发明授权

US6108259A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US6108259A
公开(公告)日：2000-08-22
申请号：US333524
申请日：1999-06-14
申请人： Soo-Hwan Choi , Young-Ho Lim
发明人： Soo-Hwan Choi , Young-Ho Lim
IPC分类号： G11C16/06 , G11C7/06 , G11C7/14 , G11C16/04 , G11C16/28 , G11C7/00
CPC分类号： G11C7/062 , G11C16/28 , G11C7/14
摘要： A semiconductor memory device includes a plurality of memory cell blocks having a plurality of memory cells, a plurality of sense amplifiers coupled to the memory cell blocks, and a reference block for generating a reference value and for providing the reference value to the sense amplifiers. Each memory cell block is coupled to at least one of the sense amplifiers. The reference block includes a reference cell for holding a predetermined reference value and a current circuit responsive to a state of the reference cell.
摘要翻译：半导体存储器件包括具有多个存储器单元的多个存储单元块，耦合到存储单元块的多个读出放大器，以及用于产生参考值并用于将该参考值提供给读出放大器的参考块。每个存储器单元块耦合到至少一个读出放大器。参考块包括用于保持预定参考值的参考单元和响应于参考单元的状态的当前电路。

6. 发明授权

US07617335B2 System having insertable and removable storage and a control method thereof 失效
标题翻译：具有可插入和可移除存储的系统及其控制方法
公开(公告)号：US07617335B2
公开(公告)日：2009-11-10
申请号：US10932482
申请日：2004-09-01
申请人： Soo-Hwan Choi
发明人： Soo-Hwan Choi
IPC分类号： G06F3/00
CPC分类号： G06F13/1694
摘要： A system including a host and a subsystem operatively coupled to the host and having a flash memory is provided. The host reads device information from a memory and provides a predetermined command to the subsystem that changes the multi-source mode to a host mode responsive to the device information. A method for controlling a subsystem and a host is additionally provided. The method includes reading device information from a memory on the subsystem and determining whether the subsystem operates in a multi-source mode responsive to the device information. The method provides a predetermined command to the subsystem so as to change the multi-source mode to a host mode responsive to the determining.
摘要翻译：提供了一种包括主机和子系统的系统，其操作上耦合到主机并具有快闪存储器。主机从存储器读取设备信息，并且向系统提供预定命令，该子系统响应于设备信息将多源模式改变为主机模式。另外提供了一种用于控制子系统和主机的方法。该方法包括从子系统中的存储器读取设备信息，并根据设备信息确定子系统是否以多源模式工作。该方法向子系统提供预定命令，以响应于确定将多源模式改变为主机模式。

7. 发明申请

US20050050235A1 System having insertable and removable storage and a control method thereof 失效
标题翻译：具有可插入和可移除存储的系统及其控制方法
公开(公告)号：US20050050235A1
公开(公告)日：2005-03-03
申请号：US10932482
申请日：2004-09-01
申请人： Soo-Hwan Choi
发明人： Soo-Hwan Choi
IPC分类号： G06F1/26 , G06F3/00 , G06F13/16 , G06K17/00 , G06K19/07 , G11C16/06 , G11C16/30
CPC分类号： G06F13/1694
摘要： A system including a host and a subsystem operatively coupled to the host and having a flash memory is provided. The host reads device information from a memory and provides a predetermined command to the subsystem that changes the multi-source mode to a host mode responsive to the device information. A method for controlling a subsystem and a host is additionally provided. The method includes reading device information from a memory on the subsystem and determining whether the subsystem operates in a multi-source mode responsive to the device information. The method provides a predetermined command to the subsystem so as to change the multi-source mode to a host mode responsive to the determining.
摘要翻译：提供了一种包括主机和子系统的系统，其操作上耦合到主机并具有快闪存储器。主机从存储器读取设备信息，并且向系统提供预定命令，该子系统响应于设备信息将多源模式改变为主机模式。另外提供了一种用于控制子系统和主机的方法。该方法包括从子系统中的存储器读取设备信息，并根据设备信息确定子系统是否以多源模式工作。该方法向子系统提供预定命令，以响应于确定将多源模式改变为主机模式。

8. 发明授权

US09136010B2 Method for generating physical identifier in storage device and machine-readable storage medium 有权
标题翻译：用于在存储设备和机器可读存储介质中生成物理标识符的方法
公开(公告)号：US09136010B2
公开(公告)日：2015-09-15
申请号：US13085052
申请日：2011-04-12
申请人： Bo-Gyeong Kang , Jung-Wan Ko , Soo-Hwan Choi , Sung-Hee Hwang , Byung-Rae Lee
发明人： Bo-Gyeong Kang , Jung-Wan Ko , Soo-Hwan Choi , Sung-Hee Hwang , Byung-Rae Lee
IPC分类号： G06F12/00 , G11C16/34 , G06F12/02 , G11C16/20 , G11C29/42 , G11C29/44 , G11C16/00
CPC分类号： G11C16/3418 , G06F12/0246 , G06F2212/7209 , G11B20/00115 , G11B20/00963 , G11B2220/60 , G11C16/00 , G11C16/20 , G11C16/349 , G11C29/42 , G11C29/44 , G11C2029/4402
摘要： A method and system for generating a physical identifier in a storage device that includes a plurality of storage regions is provided. The method includes determining a number of reference storage regions for uniquely identifying the storage device; comparing the number of reference storage regions to a threshold; generating auxiliary storage regions for uniquely identifying the storage device, such that a number of the auxiliary storage regions corresponds to a result of the comparison; generating location distribution information of the reference storage regions and auxiliary storage regions; and storing the location distribution information in the storage device.
摘要翻译：提供了一种用于在包括多个存储区域的存储设备中生成物理标识符的方法和系统。该方法包括确定用于唯一地识别存储设备的参考存储区域的数量; 将参考存储区域的数量与阈值进行比较; 产生用于唯一地识别存储设备的辅助存储区域，使得多个辅助存储区域对应于比较的结果; 产生参考存储区域和辅助存储区域的位置分布信息; 以及将所述位置分发信息存储在所述存储装置中。

9. 发明授权

US07079445B2 Flash memory pipelined burst read operation circuit, method, and system 有权
标题翻译：闪存流水线突发读操作电路，方法和系统
公开(公告)号：US07079445B2
公开(公告)日：2006-07-18
申请号：US10852841
申请日：2004-05-24
申请人： Soo-Hwan Choi , Jung-Hoon Park
发明人： Soo-Hwan Choi , Jung-Hoon Park
IPC分类号： G11C7/00
CPC分类号： G11C16/26
摘要： Method and apparatus for use with flash memory devices and systems are included among the embodiments. In exemplary systems, a pipelined burst read operation allows the device to support higher data transfer rates than are possible with prior art burst read flash memory devices. Preferably, the flash memory device supports both non-pipelined and pipelined read operations, with the read mode settable from a memory controller. Other embodiments are described and claimed.
摘要翻译：在实施例中包括用于闪存设备和系统的方法和装置。在示例性系统中，流水线突发读取操作允许设备支持比现有技术的突发读取闪存设备可能的更高的数据传输速率。优选地，闪存设备支持非流水线和流水线读取操作，读取模式可从存储器控制器设置。描述和要求保护其他实施例。

10. 发明授权

US6084800A Circuit of boosting a voltage for use in a flash memory device 失效
标题翻译：提升用于闪存器件的电压的电路
公开(公告)号：US6084800A
公开(公告)日：2000-07-04
申请号：US389279
申请日：1999-09-02
申请人： Soo-Hwan Choi , Young-Ho Lim
发明人： Soo-Hwan Choi , Young-Ho Lim
IPC分类号： G11C16/06 , G11C7/00 , G11C16/30
CPC分类号： G11C16/30
摘要： Disclosed is a circuit of boosting a voltage which comprises a driver circuit for generating a kick signal for driving word lines via row decoder circuits in an array of flash memory cells during read and program modes of operation. The driver circuit makes both electrodes of a large booster capacitor have the same voltage in order to allow a small charge pump to further pump up the word line voltage during programming.
摘要翻译：公开了一种升压电压的电路，其包括用于在读取和编程操作模式期间通过闪存单元阵列中的行解码器电路产生用于驱动字线的触发信号的驱动器电路。驱动电路使大型升压电容器的两个电极具有相同的电压，以便在编程期间允许小电荷泵进一步提高字线电压。

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