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1. 发明授权

US5536360A Method for etching boron nitride 失效
标题翻译：氮化硼蚀刻方法
公开(公告)号：US5536360A
公开(公告)日：1996-07-16
申请号：US368254
申请日：1995-01-03
申请人： Son V. Nguyen , David M. Dobuzinsky
发明人： Son V. Nguyen , David M. Dobuzinsky
IPC分类号： C04B41/91 , C30B29/38 , C30B33/00 , H01L21/306 , H01L21/308 , H01L21/311 , H01L21/3115
CPC分类号： H01L21/31116 , Y10S148/113
摘要： The subject invention provides a method of enhancing the etch rate of boron nitride which comprises doping a layer of boron nitride with an element from Group IVA of the Periodic Table of the Elements, such as silicon, carbon, or germanium. The doped boron nitride layer can be wet etched at a faster rate with hot phosphoric acid than was possible prior to doping the boron nitride.
摘要翻译：本发明提供了一种增强氮化硼蚀刻速率的方法，该方法包括用元素周期表IVA族元素（例如硅，碳或锗）掺杂一氮化硼层。掺杂的氮化硼层可以以比在掺杂氮化硼之前可能的热磷酸更快地被湿法蚀刻。

2. 发明授权

US5539154A Fluorinated silicon nitride films 失效
标题翻译：氟化氮化硅膜
公开(公告)号：US5539154A
公开(公告)日：1996-07-23
申请号：US429449
申请日：1995-04-27
申请人： Son V. Nguyen , David M. Dobuzinsky , Douglas J. Dopp , David L. Harmon
发明人： Son V. Nguyen , David M. Dobuzinsky , Douglas J. Dopp , David L. Harmon
IPC分类号： C23C14/06 , C23C16/34 , C23C16/505 , C30B25/02 , H01L21/318 , H01C7/10
CPC分类号： C23C16/505 , C23C16/345
摘要： A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride film on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4. Films prepared by the process are disclosed and their properties are described.
摘要翻译：公开了一种用于在衬底上生产氟化氮化硅膜的等离子体增强化学气相沉积工艺。该方法利用硅烷，全氟硅烷和氮气的混合物来生产具有高共形性和稳定性的薄膜。混合物中的硅烷和全氟硅烷的体积比为0.05-1。优选的硅烷是SiH 4，优选的全氟硅烷是SiF 4。公开了通过该方法制备的膜，并描述了它们的性质。

3. 发明授权

US5462812A Fluorinated silicon nitride films 失效
标题翻译：氟化氮化硅膜
公开(公告)号：US5462812A
公开(公告)日：1995-10-31
申请号：US998194
申请日：1992-12-29
申请人： Son V. Nguyen , David M. Dobuzinsky , Douglas J. Dopp , David L. Harmon
发明人： Son V. Nguyen , David M. Dobuzinsky , Douglas J. Dopp , David L. Harmon
IPC分类号： C23C14/06 , C23C16/34 , C23C16/505 , C30B25/02 , H01L21/318
CPC分类号： C23C16/505 , C23C16/345
摘要： A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride film on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4. Films prepared by the process are disclosed and their properties are described.

4. 发明授权

US5412246A Low temperature plasma oxidation process 失效
标题翻译：低温等离子体氧化工艺
公开(公告)号：US5412246A
公开(公告)日：1995-05-02
申请号：US186568
申请日：1994-01-26
申请人： David M. Dobuzinsky , David L. Harmon , Srinandan R. Kasi , Donald M. Kenney , Son V. Nguyen , Tue Nguyen , Pai-Hung Pan
发明人： David M. Dobuzinsky , David L. Harmon , Srinandan R. Kasi , Donald M. Kenney , Son V. Nguyen , Tue Nguyen , Pai-Hung Pan
IPC分类号： C23C8/36 , H01L21/31 , H01L21/316 , H01L21/321 , H01L21/8242 , H01L27/108 , H01L29/12
CPC分类号： H01L21/32105 , H01L21/02238 , H01L21/02252 , H01L21/31662 , Y10S148/118 , Y10S257/90
摘要： A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100 .ANG.. An oxide film of uniform thickness is formed by controlling the temperature, RF power, exposure time and oxygen/ozone ratio for thin gate oxide (
摘要翻译：一种在半导体器件的表面上形成薄膜的工艺。该方法包括通过等离子体增强的热氧化形成二氧化硅膜，采用臭氧和氧的混合物，其以反应器室分开产生，体积比约为1-10 / 1，优选约5-7 / 1，在一般低于440℃，优选约350-400℃的温度下进行。该方法用于在场效应晶体管的多晶硅栅上形成侧壁氧化物间隔物。在显着低于常规氧化工艺中使用的温度下实现相对较快的氧化速率，这用于减少掺杂剂从多晶硅的扩散。此外，所得膜表现出低应力，并具有多晶硅栅极的良好的共形台阶覆盖。该方法的另一个用途是生长厚度小于100安培的薄栅氧化物和氧化物 - 氮化物 - 氧化物。通过控制ULSI FET制造中薄栅氧化物（<100 ANGSTROM）应用的温度，RF功率，曝光时间和氧/臭氧比，形成均匀厚度的氧化膜。

5. 发明授权

US5204138A Plasma enhanced CVD process for fluorinated silicon nitride films 失效
标题翻译：氟化氮化硅膜的等离子体增强CVD工艺
公开(公告)号：US5204138A
公开(公告)日：1993-04-20
申请号：US814973
申请日：1991-12-24
申请人： Son V. Nguyen , David M. Dobuzinsky , Douglas J. Dopp , David L. Harmon
发明人： Son V. Nguyen , David M. Dobuzinsky , Douglas J. Dopp , David L. Harmon
IPC分类号： C23C14/06 , C23C16/34 , C23C16/505 , C30B25/02 , H01L21/318
CPC分类号： C23C16/505 , C23C16/345
摘要： A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride layer on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4.
摘要翻译：公开了一种用于在衬底上制造氟化氮化硅层的等离子体增强化学气相沉积工艺。该方法利用硅烷，全氟硅烷和氮气的混合物来制备具有高共形性和稳定性的膜。混合物中的硅烷和全氟硅烷的体积比为0.05-1。优选的硅烷是SiH 4，优选的全氟硅烷是SiF 4。

6. 发明授权

US5563105A PECVD method of depositing fluorine doped oxide using a fluorine precursor containing a glass-forming element 失效
标题翻译：使用含有玻璃形成元素的氟前体沉积氟掺杂氧化物的PECVD方法
公开(公告)号：US5563105A
公开(公告)日：1996-10-08
申请号：US316302
申请日：1994-09-30
申请人： David M. Dobuzinsky , Tetsuo Matsuda , Son V. Nguyen , James G. Ryan , Michael Shapiro
发明人： David M. Dobuzinsky , Tetsuo Matsuda , Son V. Nguyen , James G. Ryan , Michael Shapiro
IPC分类号： C23C16/30 , C23C16/40 , C23C16/505 , H01L21/31 , H01L21/316
CPC分类号： H01L21/02131 , C23C16/401 , C23C16/505 , H01L21/02274 , H01L21/31625
摘要： Fluorine-doped oxide is formed that is resistant to water absorption by the use of two sources of silicon, one being the fluorine precursor and the other being available to react with excess fluorine from the fluorine precursor, thereby reducing the number of fluorine radicals in the layer; the fluorine precursor containing a glass-forming element that combines with the other glass constituents to carry into the gas a diatomic radical containing one atom of fluorine and one atom of the glass-forming element.
摘要翻译：形成氟掺杂的氧化物，其通过使用两种硅源而具有耐吸水性，一种是氟前体，另一种可与来自氟前体的过量氟反应，从而减少氟原子的数量层; 含有玻璃形成元素的氟前体与其它玻璃成分结合，将含有一个氟原子和一个玻璃形成元素原子的双原子基团输送到气体中。

7. 发明授权

US5468687A Method of making TA.sub.2 O.sub.5 thin film by low temperature ozone plasma annealing (oxidation) 失效
标题翻译：低温臭氧等离子体退火（氧化）制备TA2O5薄膜的方法
公开(公告)号：US5468687A
公开(公告)日：1995-11-21
申请号：US281399
申请日：1994-07-27
申请人： Dan Carl , David M. Dobuzinsky , Son V. Nguyen , Tue Nguyen
发明人： Dan Carl , David M. Dobuzinsky , Son V. Nguyen , Tue Nguyen
IPC分类号： C30B29/16 , H01B3/00 , H01B3/10 , H01L21/02 , H01L21/205 , H01L21/316 , H01L21/70
CPC分类号： H01L28/40
摘要： A method for low temperature annealing (oxidation) of high dielectric constant Ta.sub.2 O.sub.5 thin films uses an ozone enhanced plasma. The films produced are especially applicable to 64 and 256 Mbit DRAM applications. The ozone enhanced plasma annealing process for thin film Ta.sub.2 O.sub.5 reduces the processing temperature to 400.degree. C. and achieves comparable film quality, making the Ta.sub.2 O.sub.5 films more suitable for Ultra-Large Scale Integration (ULSI) applications (storage dielectric for 64 and 256 Megabit DRAMs with stack capacitor structures, etc.) or others that require low temperature processing. This low temperature process is extendable to other high dc and piezoelectric thin films which may have many other applications.
摘要翻译：高介电常数Ta2O5薄膜的低温退火（氧化）方法使用臭氧增强等离子体。所制作的电影特别适用于64和256 Mbit DRAM应用。用于薄膜Ta2O5的臭氧增强等离子体退火工艺将处理温度降低到400℃，并实现了相当的膜质量，使得Ta2O5膜更适合于超大规模集成（ULSI）应用（64和256兆位DRAM的存储电介质堆叠电容器结构等）或需要低温处理的其他。这种低温工艺可扩展到可能具有许多其它应用的其它高直流和压电薄膜。

8. 发明授权

US5455204A Thin capacitor dielectric by rapid thermal processing 失效
标题翻译：薄电容电介质通过快速热处理
公开(公告)号：US5455204A
公开(公告)日：1995-10-03
申请号：US353760
申请日：1994-12-12
申请人： David M. Dobuzinsky , Son V. Nguyen , Tue Nguyen
发明人： David M. Dobuzinsky , Son V. Nguyen , Tue Nguyen
IPC分类号： H01L21/02 , H01L21/314
CPC分类号： H01L28/86 , H01L21/3144
摘要： The invention provides a continuous rapid thermal process for forming a substantially uniform oxynitride film on fingered three-dimensional silicon structures comprising cleaning of the silicon substrate and growth of silicon oxide in the presence of ozone, nitridation of the silicon oxide layer in the presence of NH.sub.3 and reoxidation of the oxynitride layer in the presence of oxygen.
摘要翻译：本发明提供了一种用于在手指三维硅结构上形成基本上均匀的氮氧化合物膜的连续快速热处理，包括在臭氧存在下清洗硅衬底和生长氧化硅，在NH 3存在下氮化氧化硅层并在氧气存在下再氧化氮氧化物层。

9. 发明授权

US5217567A Selective etching process for boron nitride films 失效
标题翻译：氮化硼薄膜的选择性蚀刻工艺
公开(公告)号：US5217567A
公开(公告)日：1993-06-08
申请号：US842663
申请日：1992-02-27
申请人： Donna R. Cote , David M. Dobuzinsky , Son V. Nguyen
发明人： Donna R. Cote , David M. Dobuzinsky , Son V. Nguyen
IPC分类号： H01L21/311 , H01L21/318
CPC分类号： H01L21/318 , H01L21/31116
摘要： Disclosed is a process for etching a film of boron nitride with high selectivity to a layer of silicon dioxide or silicon nitride. The process involves exposing the film to a plasma formed from a mixture of an oxygen-containing gas, such as oxygen, and a small amount of a fluorine-containing gas, such as CF.sub.4. The process provides a high etch rate and anisotropic profiles, as well as good uniformity.
摘要翻译：公开了以高选择性对二氧化硅或氮化硅层蚀刻氮化硼的膜的方法。该方法包括将膜暴露于由含氧气体如氧气和少量含氟气体如CF 4的混合物形成的等离子体。该方法提供了高蚀刻速率和各向异性特性，以及良好的均匀性。

10. 发明授权

US08426268B2 Embedded DRAM memory cell with additional patterning layer for improved strap formation 有权
标题翻译：具有附加图形层的嵌入式DRAM存储单元，用于改善表带形成
公开(公告)号：US08426268B2
公开(公告)日：2013-04-23
申请号：US12698293
申请日：2010-02-02
申请人： Kangguo Cheng , David M. Dobuzinsky , Byeong Y. Kim , Munir D. Naeem
发明人： Kangguo Cheng , David M. Dobuzinsky , Byeong Y. Kim , Munir D. Naeem
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10867 , H01L27/1087 , H01L29/66181
摘要： The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.
摘要翻译：本发明涉及半导体器件，更具体地说，涉及使用图形层和蚀刻顺序在半导体器件中形成存储单元的结构和方法。该方法包括在层状半导体结构中形成沟槽，每个沟槽具有邻近层间半导体结构在沟槽之间的一部分的内侧壁和与内侧壁相对的外侧壁。沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。然后蚀刻层状半导体结构。图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。通过在沟槽型存储单元制造期间在半导体结构上添加图案化层，可以减小带电阻及其变化，从而获得更好的DRAM单元操作，并且具有更少的工艺依赖性和改进的带叠层形成。

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