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    • 1. 发明授权
    • Pixel modulation apparatus and method thereof
    • 像素调制装置及其方法
    • US06963615B2
    • 2005-11-08
    • US10117204
    • 2002-04-08
    • Somei KawasakiMasami IsekiHiroyuki MaruFujio Kawano
    • Somei KawasakiMasami IsekiHiroyuki MaruFujio Kawano
    • B41J2/44H04N1/113H04N1/23H04N1/405H04N7/12
    • H04N1/4056
    • A pixel modulation apparatus for converting pixel data D composed of N1 bits to a pixel data signal composed of one bit. The pixel data D is input into the apparatus at a pixel period T0. The apparatus includes a first data conversion unit which converts the pixel data D to pixel data D1 expanded to N2 bits (N2>N1) at the period T0, a second data conversion unit which converts the pixel data D1 to pixel data D2 composed of N3/m bits at a period T0/m, a third data conversion unit which inputs n data from among the pixel data D2 and pixel data Dd2 constituting the pixel data D2 before having the period T0/m to execute logical sum operations a predetermined number (equal to or less than n) of times to convert the n data to pixel data D3 composed of N3 bits, including additional data corresponding to the predetermined number, and a fourth data conversion unit which converts the pixel data D3 to the pixel data signal composed of one bit at the period T0/m.
    • 一种像素调制装置,用于将由N 1位组成的像素数据D转换为由一位构成的像素数据信号。 像素数据D在像素周期T 0被输入到装置中。 该装置包括第一数据转换单元,其将像素数据D转换为在周期T 0处扩展为N 2位(N 2> N 1)的像素数据D 1,第二数据转换单元,将像素数据D 1转换为 在周期T 0 / m处由N 3 / m位组成的像素数据D 2,第三数据转换单元,其在具有周期之前从像素数据D 2和构成像素数据D 2的像素数据Dd 2输入n个数据 T 0 / m以执行逻辑和运算,将预定数量(等于或小于n)次以将n个数据转换为由包括与预定数量相对应的附加数据的N 3位组成的像素数据D 3,以及第四 数据转换单元,其将像素数据D 3转换为在周期T 0 / m处由一位组成的像素数据信号。
    • 3. 发明授权
    • Current programming apparatus, matrix display apparatus and current programming method
    • 当前编程设备,矩阵显示设备和当前编程方法
    • US07903053B2
    • 2011-03-08
    • US11275011
    • 2005-12-01
    • Somei KawasakiMasami IsekiFujio KawanoTakanori Yamashita
    • Somei KawasakiMasami IsekiFujio KawanoTakanori Yamashita
    • G09G3/30
    • G09G3/3283G09G3/325G09G2300/0426G09G2300/0861G09G2310/0251G09G2320/0223
    • A matrix display apparatus includes a plurality of current-driven display devices arranged along row and column directions, a first circuit provided for each of the display devices, a plurality of data lines arranged for each column, with the data lines supplying an image data signal to a plurality of pixel circuits included in each one of the columns, and a plurality of row scanning lines for transmitting a scanning signal for selecting row by row the plurality of pixel circuits. The first circuit includes a field effect transistor for supplying one of the display devices with a current, which has a control electrode and two principal electrodes, a first switch connecting the control electrode and one of the principal electrodes of the field effect transistor, and a second switch having one terminal connected to the one of the principal electrodes of the field effect transistor and having another terminal connected to one of the data lines along the column of the first circuit. The first circuits in the column are connected in successively divided manner to the plurality of the data lines through the second switch.
    • 一种矩阵显示装置,包括沿着列和列方向排列的多个电流驱动显示装置,为每个显示装置设置的第一电路,为每列布置的多条数据线,数据线提供图像数据信号 涉及包括在每列中的多个像素电路,以及多条行扫描线,用于发送用于逐行选择的多个像素电路的扫描信号。 第一电路包括用于向显示装置中的一个提供电流的场效应晶体管,其具有控制电极和两个主电极,连接控制电极和场效应晶体管的主电极之一的第一开关,以及 第二开关具有连接到场效应晶体管的一个主电极的一个端子,并且具有连接到沿着第一电路的列的数据线之一的另一端子。 列中的第一电路通过第二开关以连续分割的方式连接到多条数据线。
    • 6. 发明授权
    • Sampling device, display device using sampling device, and camera
    • 采样装置,使用采样装置的显示装置和相机
    • US08072542B2
    • 2011-12-06
    • US11693291
    • 2007-03-29
    • Masami IsekiSomei KawasakiFujio Kawano
    • Masami IsekiSomei KawasakiFujio Kawano
    • H03L7/00
    • H04N5/23293G09G3/006G09G3/3241G09G3/3283G09G2320/0233G09G2320/029H04N5/14
    • A correction sampling signal generation circuit is disposed subsequent to a plural-stage sampling signal generation circuit for sequentially generating sampling signals in response to an input timing signal, an extended sampling circuit is disposed subsequent to a plural-stage sampling circuit for sampling a video signal at timing of the sampling signal, and a data signal is sampled at timing of the sampling signal generated by the extended sampling circuit. In a timing adjustment period, the data signal for adjustment is generated, the phases of the data signal and the timing signal are relatively shifted, the outputs of the sampling circuits are supplied to a common output line through respective switches, and the phase of the optimum timing signal or the video signal is determined based on the output from the common output line.
    • 校正采样信号发生电路设置在多级采样信号产生电路之后,用于响应于输入定时信号顺序产生采样信号,扩展采样电路设置在用于对视频信号进行采样的多级采样电路之后 在采样信号的定时,并且在由扩展采样电路产生的采样信号的定时对数据信号进行采样。 在定时调整期间,产生用于调整的数据信号,数据信号和定时信号的相位相对偏移,采样电路的输出通过各个开关提供给公共输出线,并且相位 基于公共输出线的输出确定最佳定时信号或视频信号。
    • 7. 发明申请
    • SAMPLING DEVICE, DISPLAY DEVICE USING SAMPLING DEVICE, AND CAMERA
    • 采样设备,使用采样设备的显示设备和摄像机
    • US20070229692A1
    • 2007-10-04
    • US11693291
    • 2007-03-29
    • Masami ISEKISomei KawasakiFujio Kawano
    • Masami ISEKISomei KawasakiFujio Kawano
    • H04N3/14
    • H04N5/23293G09G3/006G09G3/3241G09G3/3283G09G2320/0233G09G2320/029H04N5/14
    • A correction sampling signal generation circuit is disposed subsequent to a plural-stage sampling signal generation circuit of sequentially generating sampling signals in response to an input timing signal, an extended sampling circuit is disposed subsequent to a plural-stage sampling circuit of sampling a video signal at timing of the sampling signal, and a data signal is sampled at timing of the sampling signal generated by the extended sampling circuit. In a timing adjustment period, the data signal for adjustment is generated, the phases of the data signal and the timing signal are relatively shifted, the outputs of the sampling circuits are supplied to a common output line through respective switches, and the phase of the optimum timing signal or the video signal is determined based on the output from the common output line.
    • 校正采样信号产生电路设置在响应于输入定时信号顺序产生采样信号的多级采样信号产生电路之后,扩展采样电路设置在对视频信号进行采样的多级采样电路之后 在采样信号的定时,并且在由扩展采样电路产生的采样信号的定时对数据信号进行采样。 在定时调整期间,产生用于调整的数据信号,数据信号和定时信号的相位相对偏移,采样电路的输出通过各个开关提供给公共输出线,并且相位 基于公共输出线的输出确定最佳定时信号或视频信号。
    • 8. 发明申请
    • Driver, display and recorder
    • 驱动程序,显示和录像机
    • US20050122150A1
    • 2005-06-09
    • US10994310
    • 2004-11-23
    • Masami IsekiSomei KawasakiFujio KawanoTakanori Yamashita
    • Masami IsekiSomei KawasakiFujio KawanoTakanori Yamashita
    • G09G3/30G09F9/30G09G3/20G09G3/32H03K5/153
    • G09G3/3283G09G3/3241G09G3/325G09G3/3266G09G2300/0842G09G2300/0861G09G2310/0289G09G2330/021G09G2330/026G09G2330/045
    • The present application discloses a driver having a configuration comprising: a drive transistor for supplying a current of the quantity corresponding to a gate potential, into the element as a driving current; a first switch installed in the path of the driving current passing between the element and the drive transistor, for controlling the flow of the driving current; a second switch for switching between the first state of setting the gate potential of the drive transistor and the second state of keeping the set gate potential; a circuit for supplying a signal for controlling the flow of the driving current in a restricted state to the first switch, for a predetermined period in a period after the starting the supply of the potential for driving the drive transistor from a power source and until start of driving the element in a normal operation; a circuit for supplying a signal for setting the second switch at the first state, to the second switch: and a circuit for interrupting a signal for setting the gate potential while the second switch is in the first state in the predetermined period.
    • 本申请公开了一种驱动器,其具有如下结构:驱动晶体管,用于将与栅极电位相对应的量的电流作为驱动电流提供到元件中; 安装在通过元件和驱动晶体管之间的驱动电流的路径中的第一开关,用于控制驱动电流的流动; 第二开关,用于在设置驱动晶体管的栅极电位的第一状态和保持所设置的栅极电位的第二状态之间切换; 在开始从电源驱动驱动晶体管的电位开始到起动之间的期间内,将预定时间段提供用于将限制状态下的驱动电流的流动控制到第一开关的电路 在正常操作中驱动元件; 用于向第二开关提供用于将第二开关设置的信号的电路提供给第二开关;以及用于在第二开关处于预定周期中处于第一状态时中断用于设置栅极电位的信号的电路。