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1. 发明申请

US20090237982A1 Magnetically De-Coupling Magnetic Tunnel Junctions and Bit/Word Lines for Reducing Bit Selection Errors in Spin-Momentum Transfer Switching 有权
标题翻译：磁耦合磁隧道结和位/字线，用于减少旋转动力转换切换中的位选择错误
公开(公告)号：US20090237982A1
公开(公告)日：2009-09-24
申请号：US12052326
申请日：2008-03-20
申请人： Solomon Assefa , Sivananda K. Kanakasabapathy , Janusz Jozef Nowak , Philip L. Trouilloud
发明人： Solomon Assefa , Sivananda K. Kanakasabapathy , Janusz Jozef Nowak , Philip L. Trouilloud
IPC分类号： G11C11/16 , H01L21/4763
CPC分类号： H01L27/228 , G11C11/1659 , H01L43/08 , H01L2924/0002 , H01L2924/00
摘要： Techniques for shielding magnetic memory cells from magnetic fields are presented. In accordance with aspects of the invention, a magnetic storage element is formed with at least one conductive segment electrically coupled to the magnetic storage element. At least a portion of the conductive segment is surrounded with a magnetic liner. The magnetic liner is operative to divert at least a portion of a magnetic field created by a current passing through the conductive segment away from the magnetic storage element.
摘要翻译：介绍了磁场对磁记忆体进行屏蔽的技术。根据本发明的方面，磁存储元件形成有至少一个电耦合到磁存储元件的导电段。导电段的至少一部分被磁性衬垫包围。磁性衬垫可操作以将由导电段流过的电流产生的磁场的至少一部分转移离开磁存储元件。

2. 发明授权

US07782660B2 Magnetically de-coupling magnetic memory cells and bit/word lines for reducing bit selection errors 有权
标题翻译：磁耦合磁存储单元和位/字线，以减少位选择错误
公开(公告)号：US07782660B2
公开(公告)日：2010-08-24
申请号：US12052326
申请日：2008-03-20
申请人： Solomon Assefa , Sivananda K. Kanakasabapathy , Janusz Jozef Nowak , Philip L Trouilloud
发明人： Solomon Assefa , Sivananda K. Kanakasabapathy , Janusz Jozef Nowak , Philip L Trouilloud
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , G11C11/1659 , H01L43/08 , H01L2924/0002 , H01L2924/00
摘要： Techniques for shielding magnetic memory cells from magnetic fields are presented. In accordance with aspects of the invention, a magnetic storage element is formed with at least one conductive segment electrically coupled to the magnetic storage element. At least a portion of the conductive segment is surrounded with a magnetic liner. The magnetic liner is operative to divert at least a portion of a magnetic field created by a current passing through the conductive segment away from the magnetic storage element.
摘要翻译：介绍了磁场对磁记忆体进行屏蔽的技术。根据本发明的方面，磁存储元件形成有至少一个电耦合到磁存储元件的导电段。导电段的至少一部分被磁性衬垫包围。磁性衬垫可操作以将由导电段流过的电流产生的磁场的至少一部分转移离开磁存储元件。

3. 发明授权

US08563225B2 Forming a self-aligned hard mask for contact to a tunnel junction 失效
标题翻译：形成自对准的硬掩模，用于接触隧道结
公开(公告)号：US08563225B2
公开(公告)日：2013-10-22
申请号：US12126245
申请日：2008-05-23
申请人： Solomon Assefa , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Sivananda K. Kanakasabapathy
IPC分类号： G03F7/30
CPC分类号： H01L29/82 , H01L27/222 , H01L43/08 , H01L43/12
摘要： A method of forming a hard mask in a semiconductor device which is self-aligned with a MTJ formed in the device is provided. The method includes the steps of: forming a hard mask material layer on an upper surface of a magnetic stack in the MTJ; forming an anti-reflective coating (ARC) layer on at least a portion of an upper surface of the hard mask material layer, the ARC layer being selected to be removable by a wet etch; forming a photoresist layer on at least a portion of an upper surface of the ARC layer; removing at least a portion of the photoresist layer and the ARC layer to thereby expose at least a portion of the hard mask material layer; etching the hard mask material layer to remove the exposed portion of the hard mask material layer; and performing a wet strip to remove remaining portions of the ARC layer and photoresist layer in a same processing step without interference to the magnetic stack.
摘要翻译：提供了在与设备中形成的MTJ自对准的半导体器件中形成硬掩模的方法。该方法包括以下步骤：在MTJ的磁性堆叠的上表面上形成硬掩模材料层; 在所述硬掩模材料层的上表面的至少一部分上形成抗反射涂层（ARC）层，所述ARC层被选择为通过湿法蚀刻可去除; 在所述ARC层的上表面的至少一部分上形成光致抗蚀剂层; 去除所述光致抗蚀剂层和所述ARC层的至少一部分，从而暴露所述硬掩模材料层的至少一部分; 蚀刻硬掩模材料层以去除硬掩模材料层的暴露部分; 并且在相同的处理步骤中执行湿条以去除ARC层和光致抗蚀剂层的剩余部分而不干扰磁性堆叠。

4. 发明申请

US20130069183A1 Method for Forming A Self-Aligned Hard Mask for Contact to a Tunnel Junction 有权
标题翻译：形成用于接触隧道结的自对准硬掩模的方法
公开(公告)号：US20130069183A1
公开(公告)日：2013-03-21
申请号：US13426845
申请日：2012-03-22
申请人： Solomon Assefa , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Sivananda K. Kanakasabapathy
IPC分类号： H01L29/82
CPC分类号： H01L29/82 , H01L27/222 , H01L43/08 , H01L43/12
摘要： A magnetic memory cell having a self-aligned hard mask for contact to a magnetic tunnel junction is provided. For example, a magnetic memory cell includes a magnetic storage element formed on a semiconductor substrate, and a hard mask that is self-aligned with the magnetic storage element. The hard mask includes a hard mask material layer formed on an upper surface of a magnetic stack in the magnetic storage element, an anti-reflective coating (ARC) layer formed on at least a portion of an upper surface of the hard mask material layer, wherein the ARC layer is selected to be removable by a wet etch, and a photoresist layer formed on at least a portion of an upper surface of the ARC layer. The selected portions of the ARC layer and photoresist layer are removed in a same processing step with wet etch techniques without interference to the magnetic stack.
摘要翻译：提供具有用于与磁性隧道结接触的自对准硬掩模的磁存储单元。例如，磁存储单元包括形成在半导体衬底上的磁存储元件和与磁存储元件自对准的硬掩模。硬掩模包括形成在磁性存储元件中的磁性堆叠的上表面上的硬掩模材料层，形成在硬掩模材料层的上表面的至少一部分上的抗反射涂层（ARC）层，其中所述ARC层被选择为通过湿蚀刻可去除，以及形成在所述ARC层的上表面的至少一部分上的光致抗蚀剂层。通过湿蚀刻技术在相同的处理步骤中除去ARC层和光致抗蚀剂层的选定部分，而不会干扰磁性堆叠。

5. 发明申请

US20080164617A1 Method of Forming Vertical Contacts in Integrated Circuits 有权
标题翻译：在集成电路中形成垂直触点的方法
公开(公告)号：US20080164617A1
公开(公告)日：2008-07-10
申请号：US11619623
申请日：2007-01-04
申请人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L43/12 , H01L21/76807 , H01L21/76816
摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.
摘要翻译：在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。形成覆盖在第一和第二蚀刻停止层上的ILD层。在ILD层上形成光刻掩模。光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。

6. 发明申请

US20090059656A1 Method and Structure for Improved Lithographic Alignment to Magnetic Tunnel Junctions in the Integration of Magnetic Random Access Memories 有权
标题翻译：磁性随机存取记忆集成中磁隧道结的改进光刻对准方法与结构
公开(公告)号：US20090059656A1
公开(公告)日：2009-03-05
申请号：US11850427
申请日：2007-09-05
申请人： Sivananda K. Kanakasabapathy , Solomon Assefa
发明人： Sivananda K. Kanakasabapathy , Solomon Assefa
IPC分类号： G11C11/02 , B44C1/22
CPC分类号： H01L43/12 , H01L23/544 , H01L27/222 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device.
摘要翻译：包括磁隧道结（MTJ）装置的磁存储器件包括基片和前端线（FEOL）电路。形成在VA ILD层的顶表面上方的通过级（VA）层间绝缘（ILD）层，底部导体层和形成在MTI器件上的MTJ器件。包括对准标记的对准区域延伸穿过底部导体层并向下延伸到VA ILD层的顶表面下方的装置与MJT装置并置。

7. 发明授权

US08847338B2 Method for forming a self-aligned hard mask for contact to a tunnel junction 有权
标题翻译：形成用于与隧道结接触的自对准硬掩模的方法
公开(公告)号：US08847338B2
公开(公告)日：2014-09-30
申请号：US13426845
申请日：2012-03-22
申请人： Solomon Assefa , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Sivananda K. Kanakasabapathy
IPC分类号： H01L29/84
CPC分类号： H01L29/82 , H01L27/222 , H01L43/08 , H01L43/12
摘要： A magnetic memory cell having a self-aligned hard mask for contact to a magnetic tunnel junction is provided. For example, a magnetic memory cell includes a magnetic storage element formed on a semiconductor substrate, and a hard mask that is self-aligned with the magnetic storage element. The hard mask includes a hard mask material layer formed on an upper surface of a magnetic stack in the magnetic storage element, an anti-reflective coating (ARC) layer formed on at least a portion of an upper surface of the hard mask material layer, wherein the ARC layer is selected to be removable by a wet etch, and a photoresist layer formed on at least a portion of an upper surface of the ARC layer. The selected portions of the ARC layer and photoresist layer are removed in a same processing step with wet etch techniques without interference to the magnetic stack.
摘要翻译：提供具有用于与磁性隧道结接触的自对准硬掩模的磁存储单元。例如，磁存储单元包括形成在半导体衬底上的磁存储元件和与磁存储元件自对准的硬掩模。硬掩模包括形成在磁性存储元件中的磁性堆叠的上表面上的硬掩模材料层，形成在硬掩模材料层的上表面的至少一部分上的抗反射涂层（ARC）层，其中所述ARC层被选择为通过湿蚀刻可去除，以及形成在所述ARC层的上表面的至少一部分上的光致抗蚀剂层。通过湿蚀刻技术在相同的处理步骤中除去ARC层和光致抗蚀剂层的选定部分，而不会干扰磁性堆叠。

8. 发明授权

US07825000B2 Method for integration of magnetic random access memories with improved lithographic alignment to magnetic tunnel junctions 有权
标题翻译：磁性随机存取存储器与磁性隧道结的改进的光刻对准的集成方法
公开(公告)号：US07825000B2
公开(公告)日：2010-11-02
申请号：US11850427
申请日：2007-09-05
申请人： Sivananda K. Kanakasabapathy , Solomon Assefa
发明人： Sivananda K. Kanakasabapathy , Solomon Assefa
IPC分类号： H01L21/76 , H01L21/00
CPC分类号： H01L43/12 , H01L23/544 , H01L27/222 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device.
摘要翻译：包括磁隧道结（MTJ）装置的磁存储器件包括基片和前端线（FEOL）电路。形成在VA ILD层的顶表面上方的通过级（VA）层间绝缘（ILD）层，底部导体层和形成在MTI器件上的MTJ器件。包括对准标记的对准区域延伸穿过底部导体层并向下延伸到VA ILD层的顶表面下方的装置与MJT装置并置。

9. 发明授权

US07803639B2 Method of forming vertical contacts in integrated circuits 有权
标题翻译：在集成电路中形成垂直触点的方法
公开(公告)号：US07803639B2
公开(公告)日：2010-09-28
申请号：US11619623
申请日：2007-01-04
申请人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
IPC分类号： H01L21/00 , H01L21/4763 , H01L21/44
CPC分类号： H01L43/12 , H01L21/76807 , H01L21/76816
摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.
摘要翻译：在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。形成覆盖在第一和第二蚀刻停止层上的ILD层。在ILD层上形成光刻掩模。光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。

10. 发明申请

US20090291388A1 Method for Forming a Self-Aligned Hard Mask for Contact to a Tunnel Junction 失效
标题翻译：形成用于接触隧道结的自对准硬掩模的方法
公开(公告)号：US20090291388A1
公开(公告)日：2009-11-26
申请号：US12126245
申请日：2008-05-23
申请人： Solomon Assefa , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Sivananda K. Kanakasabapathy
IPC分类号： G03F7/004 , G03F7/26
CPC分类号： H01L29/82 , H01L27/222 , H01L43/08 , H01L43/12
摘要： A method of forming a hard mask in a semiconductor device which is self-aligned with a MTJ formed in the device is provided. The method includes the steps of: forming a hard mask material layer on an upper surface of a magnetic stack in the MTJ; forming an anti-reflective coating (ARC) layer on at least a portion of an upper surface of the hard mask material layer, the ARC layer being selected to be removable by a wet etch; forming a photoresist layer on at least a portion of an upper surface of the ARC layer; removing at least a portion of the photoresist layer and the ARC layer to thereby expose at least a portion of the hard mask material layer; etching the hard mask material layer to remove the exposed portion of the hard mask material layer; and performing a wet strip to remove remaining portions of the ARC layer and photoresist layer in a same processing step without interference to the magnetic stack.
摘要翻译：提供了在与设备中形成的MTJ自对准的半导体器件中形成硬掩模的方法。该方法包括以下步骤：在MTJ的磁性堆叠的上表面上形成硬掩模材料层; 在所述硬掩模材料层的上表面的至少一部分上形成抗反射涂层（ARC）层，所述ARC层被选择为通过湿法蚀刻可去除; 在所述ARC层的上表面的至少一部分上形成光致抗蚀剂层; 去除所述光致抗蚀剂层和所述ARC层的至少一部分，从而暴露所述硬掩模材料层的至少一部分; 蚀刻硬掩模材料层以去除硬掩模材料层的暴露部分; 并且在相同的处理步骤中执行湿条以去除ARC层和光致抗蚀剂层的剩余部分而不干扰磁性堆叠。

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