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1. 发明授权

US08164128B2 Magnetic devices and techniques for formation thereof 失效
标题翻译：磁性器件及其形成技术
公开(公告)号：US08164128B2
公开(公告)日：2012-04-24
申请号：US11926845
申请日：2007-10-29
申请人： Sivananda K. Kanakasabapathy , Michael C. Gaidis
发明人： Sivananda K. Kanakasabapathy , Michael C. Gaidis
IPC分类号： H01L29/94
CPC分类号： H01L43/12 , H01L21/76897 , H01L27/222 , H01L43/08 , H01L2924/3011
摘要： Techniques for forming a magnetic device are provided. In one aspect, a magnetic device includes a magnetic tunnel junction and a dielectric layer formed over at least a portion of the magnetic tunnel junction. The dielectric layer is configured to have an underlayer proximate to the magnetic tunnel junction, and an overlayer on a side of the underlayer opposite the magnetic tunnel junction. The magnetic device further includes a via hole running substantially vertically through the dielectric layer and being self-aligned with the magnetic tunnel junction.
摘要翻译：提供了用于形成磁性装置的技术。在一个方面，磁性装置包括形成在磁性隧道结的至少一部分上的磁性隧道结和介电层。介电层被配置为具有靠近磁性隧道结的底层，以及与该底层的与磁性隧道结相对的一侧上的覆盖层。磁性器件还包括通孔，该通孔基本垂直穿过介电层并与磁性隧道结自对准。

2. 发明授权

US07381343B2 Hard mask structure for patterning of materials 有权
标题翻译：用于图案化材料的硬掩模结构
公开(公告)号：US07381343B2
公开(公告)日：2008-06-03
申请号：US11177008
申请日：2005-07-08
申请人： Michael C. Gaidis , Sivananda K. Kanakasabapathy , Eugene J. O'Sullivan
发明人： Michael C. Gaidis , Sivananda K. Kanakasabapathy , Eugene J. O'Sullivan
IPC分类号： B44C1/22 , H01L21/302
CPC分类号： H01L43/12 , H01L21/0332 , H01L21/0337 , H01L27/11507 , H01L28/65
摘要： Techniques for magnetic device fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure is formed on at least one surface of the material to be patterned. The hard mask structure is configured to have a base, proximate to the material, and a top opposite the base. The base has one or more lateral dimensions that are greater than one or more lateral dimensions of the top of the hard mask structure, such that at least one portion of the base extends out laterally a substantial distance beyond the top. The top of the hard mask structure is at a greater vertical distance from the material being etched than the base. The material is etched.
摘要翻译：提供了磁性器件制造技术。一方面，图案化至少一种，例如非挥发性材料的方法包括以下步骤。在待图案化材料的至少一个表面上形成硬掩模结构。硬掩模结构被配置为具有靠近材料的基部和与基部相对的顶部。基座具有大于硬掩模结构的顶部的一个或多个横向尺寸的一个或多个横向尺寸，使得基部的至少一部分横向延伸超过顶部的实质距离。硬掩模结构的顶部距离被蚀刻的材料比基底更大的垂直距离。材料被蚀刻。

3. 发明授权

US07033881B2 Method for fabricating magnetic field concentrators as liners around conductive wires in microelectronic devices 有权
标题翻译：制造磁场集中器作为微电子器件中导线周围的衬垫的方法
公开(公告)号：US07033881B2
公开(公告)日：2006-04-25
申请号：US10710044
申请日：2004-06-15
申请人： Michael C. Gaidis , Phillip L. Trouilloud , Sivananda K. Kanakasabapathy , David W. Abraham
发明人： Michael C. Gaidis , Phillip L. Trouilloud , Sivananda K. Kanakasabapathy , David W. Abraham
IPC分类号： H01L21/8242
CPC分类号： H01L43/12 , G11C11/15 , G11C11/16 , H01L27/222
摘要： In an MRAM cell, the writing current is encased in a low-reluctance material that is treated in one of several ways to render the material closest to the storage element ineffective to carry magnetic flux, thereby establishing a horseshoe-shaped cross section that focuses the flux toward the storage element.
摘要翻译：在MRAM单元中，写入电流被封装在低磁阻材料中，其以几种方式之一进行处理，以使得最靠近存储元件的材料无效地携带磁通量，从而建立了马蹄形横截面，其将向储存元件的通量。

4. 发明授权

US07550044B2 Hard mask structure for patterning of materials 有权
标题翻译：用于图案化材料的硬掩模结构
公开(公告)号：US07550044B2
公开(公告)日：2009-06-23
申请号：US12099441
申请日：2008-04-08
申请人： Michael C. Gaidis , Sivananda K. Kanakasabapathy , Eugene J. O'Sullivan
发明人： Michael C. Gaidis , Sivananda K. Kanakasabapathy , Eugene J. O'Sullivan
IPC分类号： B05C1/00 , B44C1/22
CPC分类号： H01L43/12 , H01L21/0332 , H01L21/0337 , H01L27/11507 , H01L28/65
摘要： Techniques for magnetic device fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure is formed on at least one surface of the material to be patterned. The hard mask structure is configured to have a base, proximate to the material, and a top opposite the base. The base has one or more lateral dimensions that are greater than one or more lateral dimensions of the top of the hard mask structure, such that at least one portion of the base extends out laterally a substantial distance beyond the top. The top of the hard mask structure is at a greater vertical distance from the material being etched than the base. The material is etched.
摘要翻译：提供了磁性器件制造技术。一方面，图案化至少一种，例如非挥发性材料的方法包括以下步骤。在待图案化材料的至少一个表面上形成硬掩模结构。硬掩模结构被配置为具有靠近材料的基部和与基部相对的顶部。基座具有大于硬掩模结构的顶部的一个或多个横向尺寸的一个或多个横向尺寸，使得基部的至少一部分横向延伸超过顶部的实质距离。硬掩模结构的顶部距离被蚀刻的材料比基底更大的垂直距离。材料被蚀刻。

5. 发明申请

US20080164617A1 Method of Forming Vertical Contacts in Integrated Circuits 有权
标题翻译：在集成电路中形成垂直触点的方法
公开(公告)号：US20080164617A1
公开(公告)日：2008-07-10
申请号：US11619623
申请日：2007-01-04
申请人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L43/12 , H01L21/76807 , H01L21/76816
摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.
摘要翻译：在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。形成覆盖在第一和第二蚀刻停止层上的ILD层。在ILD层上形成光刻掩模。光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。

6. 发明申请

US20080185101A1 Hard Mask Structure for Patterning of Materials 有权
标题翻译：材料图案的硬掩模结构
公开(公告)号：US20080185101A1
公开(公告)日：2008-08-07
申请号：US12099441
申请日：2008-04-08
申请人： Michael C. Gaidis , Sivananda K. Kanakasabapathy , Eugene J. O'Sullivan
发明人： Michael C. Gaidis , Sivananda K. Kanakasabapathy , Eugene J. O'Sullivan
IPC分类号： H01L21/306
CPC分类号： H01L43/12 , H01L21/0332 , H01L21/0337 , H01L27/11507 , H01L28/65
摘要： Techniques for magnetic device fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure is formed on at least one surface of the material to be patterned. The hard mask structure is configured to have a base, proximate to the material, and a top opposite the base. The base has one or more lateral dimensions that are greater than one or more lateral dimensions of the top of the hard mask structure, such that at least one portion of the base extends out laterally a substantial distance beyond the top. The top of the hard mask structure is at a greater vertical distance from the material being etched than the base. The material is etched.
摘要翻译：提供了磁性器件制造技术。一方面，图案化至少一种，例如非挥发性材料的方法包括以下步骤。在待图案化材料的至少一个表面上形成硬掩模结构。硬掩模结构被配置为具有靠近材料的基部和与基部相对的顶部。基座具有大于硬掩模结构的顶部的一个或多个横向尺寸的一个或多个横向尺寸，使得基部的至少一部分横向延伸超过顶部的实质距离。硬掩模结构的顶部距离被蚀刻的材料比基底更大的垂直距离。材料被蚀刻。

7. 发明授权

US06933204B2 Method for improved alignment of magnetic tunnel junction elements 有权
标题翻译：改善磁性隧道结元件对准的方法
公开(公告)号：US06933204B2
公开(公告)日：2005-08-23
申请号：US10605604
申请日：2003-10-13
申请人： Chandrasekhar Sarma , Sivananda K. Kanakasabapathy , Ihar Kasko , Greg Costrini , John P. Hummel , Michael C. Gaidis
发明人： Chandrasekhar Sarma , Sivananda K. Kanakasabapathy , Ihar Kasko , Greg Costrini , John P. Hummel , Michael C. Gaidis
IPC分类号： G03F9/00 , H01L21/76 , H01L23/544 , H01L27/22
CPC分类号： H01L27/222 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for aligning an opaque, active device in a semiconductor structure includes forming an opaque layer over an optically transparent layer formed on a lower metallization level, the lower metallization level including one or more alignment marks formed therein. A portion of the opaque layer is patterned and opened corresponding to the location of the one or more alignment marks in the lower metallization level so as to render the one or more alignment marks optically visible. The opaque layer is then patterned with respect to the lower metallization level, using the optically visible one or more alignment marks.
摘要翻译：用于对准半导体结构中的不透明有源器件的方法包括在形成在下金属化层上的光学透明层上形成不透明层，所述下金属化层包括其中形成的一个或多个对准标记。对应于下部金属化水平中的一个或多个对准标记的位置，对不透明层的一部分进行图案化和打开，以便使一个或多个对准标记光学可见。然后使用光学可见的一个或多个对准标记，相对于较低的金属化水平对不透明层进行图案化。

8. 发明授权

US07399646B2 Magnetic devices and techniques for formation thereof 失效
标题翻译：磁性器件及其形成技术
公开(公告)号：US07399646B2
公开(公告)日：2008-07-15
申请号：US11209951
申请日：2005-08-23
申请人： Sivananda K. Kanakasabapathy , Michael C. Gaidis
发明人： Sivananda K. Kanakasabapathy , Michael C. Gaidis
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L21/76897 , H01L27/222 , H01L43/08 , H01L2924/3011
摘要： Techniques for forming a magnetic device are provided. In one aspect, a method of forming a via hole self-aligned with a magnetic device comprises the following steps. A dielectric layer is formed over at least a portion of the magnetic device. The dielectric layer is configured to have an underlayer proximate to the magnetic device which comprises a first material, and an overlayer on a side of the underlayer opposite the magnetic device which comprises a second material. The first material is different from the second material. In a first etching phase, a first etchant is used to etch the dielectric layer, beginning with the overlayer, and through the overlayer. In a second etching phase, a second etchant which is selective for etching the underlayer is used to etch the dielectric layer through the underlayer.
摘要翻译：提供了用于形成磁性装置的技术。一方面，形成与磁性装置自对准的通孔的方法包括以下步骤。在磁性器件的至少一部分上形成电介质层。电介质层被配置为具有靠近磁性装置的底层，其包括第一材料，并且在与包括第二材料的磁性装置相对的底层的一侧上的覆盖层。第一种材料与第二种材料不同。在第一蚀刻阶段中，使用第一蚀刻剂来从覆盖层开始并通过覆盖层来蚀刻介电层。在第二蚀刻阶段中，使用用于蚀刻底层的第二蚀刻剂来蚀刻通过底层的介电层。

9. 发明授权

US07803639B2 Method of forming vertical contacts in integrated circuits 有权
标题翻译：在集成电路中形成垂直触点的方法
公开(公告)号：US07803639B2
公开(公告)日：2010-09-28
申请号：US11619623
申请日：2007-01-04
申请人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
IPC分类号： H01L21/00 , H01L21/4763 , H01L21/44
CPC分类号： H01L43/12 , H01L21/76807 , H01L21/76816
摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.
摘要翻译：在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。形成覆盖在第一和第二蚀刻停止层上的ILD层。在ILD层上形成光刻掩模。光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。

10. 发明授权

US08835232B2 Low external resistance ETSOI transistors 有权
标题翻译：低外部电阻ETSOI晶体管
公开(公告)号：US08835232B2
公开(公告)日：2014-09-16
申请号：US13606694
申请日：2012-09-07
申请人： Hemanth Jagannathan , Sivananda K. Kanakasabapathy
发明人： Hemanth Jagannathan , Sivananda K. Kanakasabapathy
IPC分类号： H01L29/78
CPC分类号： H01L27/1203 , H01L21/823814 , H01L21/823842 , H01L29/42384 , H01L29/4908
摘要： A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.
摘要翻译：在绝缘体上半导体（SOI）基板上形成一次性介质结构，使得一次性介质结构的所有物理暴露表面都是电介质表面。半导体材料选择性地沉积在半导体表面上，同时抑制任何半导体材料在电介质表面上的沉积。在形成至少一个栅极间隔物和源极和漏极区域之后，平坦化介电层被沉积并平坦化以物理暴露一次性介电结构的顶表面。一次性介质结构被包括栅极电介质和栅极导体部分的替换栅极堆叠替代。可以提供较低的外部电阻，而不会影响场效应晶体管器件的短沟道性能。

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