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1. 发明授权

US07033881B2 Method for fabricating magnetic field concentrators as liners around conductive wires in microelectronic devices 有权
标题翻译：制造磁场集中器作为微电子器件中导线周围的衬垫的方法
公开(公告)号：US07033881B2
公开(公告)日：2006-04-25
申请号：US10710044
申请日：2004-06-15
申请人： Michael C. Gaidis , Phillip L. Trouilloud , Sivananda K. Kanakasabapathy , David W. Abraham
发明人： Michael C. Gaidis , Phillip L. Trouilloud , Sivananda K. Kanakasabapathy , David W. Abraham
IPC分类号： H01L21/8242
CPC分类号： H01L43/12 , G11C11/15 , G11C11/16 , H01L27/222
摘要： In an MRAM cell, the writing current is encased in a low-reluctance material that is treated in one of several ways to render the material closest to the storage element ineffective to carry magnetic flux, thereby establishing a horseshoe-shaped cross section that focuses the flux toward the storage element.
摘要翻译：在MRAM单元中，写入电流被封装在低磁阻材料中，其以几种方式之一进行处理，以使得最靠近存储元件的材料无效地携带磁通量，从而建立了马蹄形横截面，其将向储存元件的通量。

2. 发明申请

US20080220374A1 METHOD AND STRUCTURE FOR IMPROVED ALIGNMENT IN MRAM INTEGRATION 审中-公开
公开(公告)号：US20080220374A1
公开(公告)日：2008-09-11
申请号：US12125099
申请日：2008-05-22
申请人： Sivananda K. Kanakasabapathy , David W. Abraham
发明人： Sivananda K. Kanakasabapathy , David W. Abraham
IPC分类号： G03F7/26
CPC分类号： H01L23/544 , H01L27/222 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.

3. 发明申请

US20080160644A1 METHOD AND STRUCTURE FOR IMPROVED ALIGNMENT IN MRAM INTEGRATION 审中-公开
公开(公告)号：US20080160644A1
公开(公告)日：2008-07-03
申请号：US12050281
申请日：2008-03-18
申请人： Sivananda K. Kanakasabapathy , David W. Abraham
发明人： Sivananda K. Kanakasabapathy , David W. Abraham
IPC分类号： H01L21/66
CPC分类号： H01L23/544 , H01L27/222 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.

4. 发明授权

US07507633B2 Method and structure for improved alignment in MRAM integration 有权
标题翻译：改善MRAM集成对齐的方法和结构
公开(公告)号：US07507633B2
公开(公告)日：2009-03-24
申请号：US11369516
申请日：2006-03-07
申请人： Sivananda K. Kanakasabapathy , David W. Abraham
发明人： Sivananda K. Kanakasabapathy , David W. Abraham
IPC分类号： H01L21/76
CPC分类号： H01L23/544 , H01L27/222 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.
摘要翻译：用于实现半导体器件结构的对准的方法包括在该结构的较低级别内形成第一组和第二组对准标记，第二组对准标记与第一组对准标记相邻。在较低层上形成不透明层，包括第一组和第二组对准标记。对应于所述第一组对准标记的位置的不透明层的一部分被打开，以使第一组光学可见，而第二组对准标记最初保持被不透明层覆盖。使用光学可见的第一组对准标记图案化不透明层，其中在第一组在不透明层的图案化期间第一组变得损坏的情况下，第二组对准标记保持可用于随后的对准操作。

5. 发明授权

US07723813B2 Method and structure for improved alignment in MRAM integration 有权
标题翻译：改善MRAM集成对齐的方法和结构
公开(公告)号：US07723813B2
公开(公告)日：2010-05-25
申请号：US12050293
申请日：2008-03-18
申请人： Sivananda K. Kanakasabapathy , David W. Abraham
发明人： Sivananda K. Kanakasabapathy , David W. Abraham
IPC分类号： H01L23/544 , H01L29/82
CPC分类号： H01L23/544 , H01L27/222 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.
摘要翻译：用于实现半导体器件结构的对准的方法包括在该结构的较低级别内形成第一组和第二组对准标记，第二组对准标记与第一组对准标记相邻。在较低层上形成不透明层，包括第一组和第二组对准标记。对应于所述第一组对准标记的位置的不透明层的一部分被打开，以使第一组光学可见，而第二组对准标记最初保持被不透明层覆盖。使用光学可见的第一组对准标记图案化不透明层，其中在第一组在不透明层的图案化期间第一组变得损坏的情况下，第二组对准标记保持可用于随后的对准操作。

6. 发明授权

US07112861B2 Magnetic tunnel junction cap structure and method for forming the same 有权
标题翻译：磁隧道结盖结构及其形成方法
公开(公告)号：US07112861B2
公开(公告)日：2006-09-26
申请号：US10709573
申请日：2004-05-14
申请人： Sivananda K. Kanakasabapathy , David W. Abraham , Ulrich Klostermann
发明人： Sivananda K. Kanakasabapathy , David W. Abraham , Ulrich Klostermann
IPC分类号： G01R33/09
CPC分类号： H01L43/12
摘要： A a magnetic random access memory (MRAM) device includes a cap layer formed over a magnetic tunnel junction (MTJ) stack layer, an etch stop layer formed over the first cap layer, and a hardmask layer formed over the etch stop layer. The etch stop layer is selected from a material such that an etch chemistry used for removing the hardmask layer has selectivity against etching the etch stop layer material.
摘要翻译：磁性随机存取存储器（MRAM）器件包括形成在磁隧道结（MTJ）堆叠层上的覆盖层，形成在第一覆盖层上的蚀刻停止层，以及形成在蚀刻停止层上的硬掩模层。蚀刻停止层选自材料，使得用于去除硬掩模层的蚀刻化学性质对蚀刻停止层材料的蚀刻具有选择性。

7. 发明申请

US20080157156A1 METHOD AND STRUCTURE FOR IMPROVED ALIGNMENT IN MRAM INTEGRATION 有权
标题翻译：在MRAM集成中改进对准的方法和结构
公开(公告)号：US20080157156A1
公开(公告)日：2008-07-03
申请号：US12050293
申请日：2008-03-18
申请人： Sivananda K. Kanakasabapathy , David W. Abraham
发明人： Sivananda K. Kanakasabapathy , David W. Abraham
IPC分类号： H01L29/00
CPC分类号： H01L23/544 , H01L27/222 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.
摘要翻译：用于实现半导体器件结构的对准的方法包括在该结构的较低级别内形成第一组和第二组对准标记，第二组对准标记与第一组对准标记相邻。在较低层上形成不透明层，包括第一组和第二组对准标记。对应于所述第一组对准标记的位置的不透明层的一部分被打开，以使第一组光学可见，而第二组对准标记最初保持被不透明层覆盖。使用光学可见的第一组对准标记图案化不透明层，其中在第一组在不透明层的图案化期间第一组变得损坏的情况下，第二组对准标记保持可用于随后的对准操作。

8. 发明授权

US08835232B2 Low external resistance ETSOI transistors 有权
标题翻译：低外部电阻ETSOI晶体管
公开(公告)号：US08835232B2
公开(公告)日：2014-09-16
申请号：US13606694
申请日：2012-09-07
申请人： Hemanth Jagannathan , Sivananda K. Kanakasabapathy
发明人： Hemanth Jagannathan , Sivananda K. Kanakasabapathy
IPC分类号： H01L29/78
CPC分类号： H01L27/1203 , H01L21/823814 , H01L21/823842 , H01L29/42384 , H01L29/4908
摘要： A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.
摘要翻译：在绝缘体上半导体（SOI）基板上形成一次性介质结构，使得一次性介质结构的所有物理暴露表面都是电介质表面。半导体材料选择性地沉积在半导体表面上，同时抑制任何半导体材料在电介质表面上的沉积。在形成至少一个栅极间隔物和源极和漏极区域之后，平坦化介电层被沉积并平坦化以物理暴露一次性介电结构的顶表面。一次性介质结构被包括栅极电介质和栅极导体部分的替换栅极堆叠替代。可以提供较低的外部电阻，而不会影响场效应晶体管器件的短沟道性能。

9. 发明申请

US20140024209A1 METHOD OF SIMULTANEOUSLY FORMING MULTIPLE STRUCTURES HAVING DIFFERENT CRITICAL DIMENSIONS USING SIDEWALL TRANSFER 有权
标题翻译：同时形成具有不同关键尺寸的多个结构的方法
公开(公告)号：US20140024209A1
公开(公告)日：2014-01-23
申请号：US13552035
申请日：2012-07-18
申请人： Ryan O. Jung , Sivananda K. Kanakasabapathy
发明人： Ryan O. Jung , Sivananda K. Kanakasabapathy
IPC分类号： H01L21/28
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32139 , H01L21/76224 , H01L21/823456 , H01L29/66575 , H01L29/78
摘要： A method of forming multiple different width dimension features simultaneously. The method includes forming multiple sidewall spacers of different widths formed from different combinations of conformal layers on different mandrels, removing the mandrels, and simultaneously transferring the pattern of the different sidewall spacers into an underlying layer.
摘要翻译：同时形成多个不同宽度尺寸特征的方法。该方法包括形成由不同心轴上的适形层的不同组合形成的不同宽度的多个侧壁间隔物，去除心轴，以及同时将不同侧壁间隔物的图案转移到下面的层中。

10. 发明申请

US20140023834A1 IMAGE TRANSFER PROCESS EMPLOYING A HARD MASK LAYER 审中-公开
标题翻译：使用硬掩模层的图像传输过程
公开(公告)号：US20140023834A1
公开(公告)日：2014-01-23
申请号：US13571496
申请日：2012-08-10
申请人： Ryan O. Jung , Sivananda K. Kanakasabapathy , Yunpeng Yin
发明人： Ryan O. Jung , Sivananda K. Kanakasabapathy , Yunpeng Yin
IPC分类号： B32B3/10
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/31144 , Y10T428/24802
摘要： At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed. An overlying structure including a second pattern that includes at least one blocking area is formed over said patterned mask layer. Portions of said patterned mask layer that do not underlie said blocking area are removed. The remaining portions of the patterned mask layer include a composite pattern that is an intersection of the first pattern and the second pattern. The patterned mask layer includes a dielectric material or a metallic material, and thus, enables high fidelity pattern transfer into an underlying material layer.
摘要翻译：在衬底上形成的至少一个掩模层包括电介质材料和金属材料中的至少一种。通过在所述至少一个掩模层之一中形成第一图案，形成包括所述第一图案的图案化掩模层。在所述图案化掩模层上形成包括包括至少一个阻挡区域的第二图案的覆盖结构。除去不在所述阻挡区域下面的所述图案化掩模层的部分被去除。图案化掩模层的其余部分包括作为第一图案和第二图案的交叉的复合图案。图案化掩模层包括电介质材料或金属材料，因此能够将高保真图案转移到下面的材料层中。

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